Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer and including a channel region sandwiched between a first source/drain region and a second source/drain region, a first plurality of nanostructures disposed over the channel region, a first leakage block layer over the first source/drain region, a second leakage block layer over the second source/drain region, a dielectric layer on the first leakage block layer, a first source/drain feature on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures, and a second source/drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures. The first leakage block layer and the second leakage block layer includes an undoped semiconductor material.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source/drain regions separated by channel regions. Gates at the channel regions formed fully around every surface of the channel region as gate-all-around (GAA) structures separated from channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes connected to the second source/drain regions and digit lines connected to the first source/drain regions.

A semiconductor device includes: an active region on a substrate; a gate structure intersecting the active region and including a gate electrode; a source/drain region on the active region; a first contact structure on and connected to the source/drain region; first and second insulating layers on the gate and first contact structures; a second contact structure connected to the gate electrode and including: a first contact via in the first insulating layer; and a first conductive cap layer in the second insulating layer and on the first contact via; a via structure connected to the first contact structure, the via structure including: a second contact via in the first insulating layer; and a second conductive cap layer in the second insulating layer and on the second contact via; and interconnection lines on the second insulating layer connected to the second contact structure and the via structure.

A semiconductor device may include a substrate including an active pattern, a lower power line in a lower portion of the substrate, a channel pattern on the active pattern and including a plurality of semiconductor patterns, which are stacked and include a first semiconductor pattern at the lowermost level, a gate electrode crossing the active pattern and including a first inner gate electrode between the active pattern and the first semiconductor pattern, source/drain patterns on the substrate, backside contacts connecting the lower power line to the source/drain patterns, and a filler structure between adjacent backside contacts among the backside contacts. The filler structure may include a filling pattern and a liner. The filling pattern may include a contact portion on a filler portion, and the liner may cover opposite side surfaces of the filler portion. The contact portion may be in direct contact with the substrate.

A method of forming a semiconductor device includes: forming a device layer that includes nanostructures and a gate structure around the nanostructures; forming a first interconnect structure on a front-side of the device layer; and forming a second interconnect structure on a backside of the device layer, which includes: forming a dielectric layer along the backside of the device layer using a first dielectric material; forming a first conductive feature and a second conductive feature in the dielectric layer; form an opening in the dielectric layer between the first and the second conductive features; forming a first barrier layer and a second barrier layer along a first sidewall of the first conductive feature and along a second sidewall of the second conductive feature, respectively; and forming a second dielectric material different from the first dielectric material in the opening between the first barrier layer and the second barrier layer.

A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.

A semiconductor device may include an active pattern on a substrate, first to third gate electrodes on the active pattern, a first source/drain region and a first source/drain contact between the first and second gate electrodes, a second source/drain region and a second source/drain contact between the second and third gate electrodes, a gate spacer on both sidewalls of the second gate electrode, a first interlayer insulating layer covering the first and second source/drain regions, and a second interlayer insulating layer in contact with at least a portion of sidewalls of the first source/drain contact. A lower surface of the second interlayer insulating layer may contact upper surfaces of the second gate electrode, the second source/drain contact, and the gate spacer between the second gate electrode and the second source/drain contact.

A semiconductor device includes an insulating base layer, a fin-type pattern on the insulating base layer and extending in a first direction, a plurality of channel structures on the fin-type pattern and spaced apart from each other in the first direction, each of the plurality of channel structures including a plurality of channel layers spaced apart from each other in a second direction that is perpendicular to the first direction, a plurality of gate structures respectively on the plurality of channel structures and extending in a third direction intersecting the first direction, source/drain patterns including a first source/drain pattern that is connected to side surfaces of some of the plurality of channel structures, internal spacers between the plurality of gate structures and the source/drain patterns, and a plurality of bottom isolation patterns respectively below the plurality of gate structures and between the insulating base layer and the fin-type pattern.

The present disclosure provides a semiconductor device, a method, and an electronic apparatus. The device includes: a substrate; a channel layer stacking portion including multiple channel layers along a thickness direction of the substrate, a length direction of the channel layer is perpendicular to the thickness direction of the substrate, and the channel layer includes a first end, a middle section and a second end along the length direction; a gate-all-around surrounding the middle section; a source/drain functional portion; and a spacer structure including first and second spacers. The first spacer is between first ends and second ends of adjacent channel layers, and includes a cavity. The second spacer is on a side of the channel layer stacking portion away from the substrate and on both sides of the gate-all-around along the length direction. A dielectric constant of the first spacer is greater than that of the second spacer.

Provided is a semiconductor device and method of manufacturing same, the semiconductor device including: a plurality of active patterns on a substrate; a source/drain pattern on the substrate; a power rail in the substrate; a pillar pattern between the plurality of active patterns; a channel pattern on the pillar pattern; a backside conductive contact between the source/drain pattern and the power rail; and a liner pattern on the pillar pattern, wherein the liner pattern includes: a first portion that covers a top surface of a lower portion of the backside conductive contact; and a second portion that extends from the first portion and along a sidewall of the lower portion of the backside conductive contact.