A High Electron Mobility Transistor, (HEMT), structure having a gate, a source and a drain, the HEMT structure including a depletion-mode transistor having a breakdown voltage, current limiting means arranged for ensuring that a drain source current of the HEMT structure, in an off-state of the HEMT structure, is at most 20 nA/mm, being a current per unit gate length of the depletion-mode transistor, the HEMT structure can include just the depletion-mode transistor or a cascode configuration of a depletion-mode transistor with an enhancement mode transistor.

N-polar HEMT structures and methods of forming HEMT structures. An example semiconductor device includes a III-N material structure, comprising: a III-N backbarrier layer; a III-N channel layer over an N-face of the III-N backbarrier layer; and an n+ III-N etch stop layer over an N-face of the III-N channel layer. The semiconductor device includes: a gate region between a source region and a drain region; a source contact over the n+ III-Netch stop layer in the source region; a drain contact over the n+ III-N etch stop layer in the drain region; a 2DEG in the III-N channel layer adjacent to an interface between the III-N channel layer and the III-N backbarrier layer; a channel recess etched through the n+ III-N etch stop layer between the source region and the drain region; and a gate recess in the channel layer and a gate contact in the gate recess.

According to one embodiment, a wafer includes a base, a first semiconductor layer including Al.sub.x1Ga.sub.1-x1N (0x1<1), and a second semiconductor layer including Al.sub.x2Ga.sub.1-x2N (x1<x2<1). The first semiconductor layer is between the base and the second semiconductor layer. The second semiconductor layer includes first to fourth regions. The first region is between the first semiconductor layer and the third region. The second region is between the first region and the third region. The fourth region is between the first semiconductor layer and the first region. A second Al composition ratio in the second region is lower than a third Al composition ratio in the third region. A first Al composition ratio in the first region is higher than the second Al composition ratio.

According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, and a first insulating member. The semiconductor member includes a first semiconductor region including Al.sub.x1Ga.sub.1x1N (0x1<1), a second semiconductor region including Al.sub.x2Ga.sub.1x2N (0<x2<1, x1<x2), and a third semiconductor region including Al.sub.x3Ga.sub.1x3N (0<x3<1, x1<x3). The first semiconductor region includes first and semiconductor portions. The second semiconductor region includes third and fourth semiconductor portions. The first insulating member includes first to third insulating regions. At least a part of the second insulating region is between the first semiconductor portion and the first electrode portion of the third electrode. At least a part of the first insulating region is between the fourth partial region and the fifth partial region in the first direction.

A semiconductor device includes a substrate; a gallium nitride layer located on a non-polar surface of the substrate, the gallium nitride layer including a plurality of fin parts separated from each other in a first direction parallel to a c-axis direction, the plurality of fin parts extending in a second direction; an electron supply layer located at a Ga-surface of at least one of the fin parts; a source finger part extending in the first direction and contacting the electron supply layer; a drain finger part extending in the first direction and contacting the electron supply layer, the drain finger part being separated from the source finger part in the second direction; and a gate electrode positioned between the source finger part and the drain finger part, the gate electrode facing the electron supply layer in the first direction.

A nanochannel GaN-based device includes: a substrate layer, a nucleation layer, a buffer layer, a channel region, an insertion layer, a barrier layer, a cap layer, a first highly n.sup.+-doped material layer, a second n.sup.+-doped material layer, a source electrode, a drain electrode, and a gate electrode. A first arrayed pattern edge is formed on a side of the first n.sup.+-doped material layer facing towards the drain electrode. A second arrayed pattern edge is formed on a side of the second n.sup.+-doped material layer facing towards the source electrode. A part of the channel region, the insertion layer, the barrier layer and the cap layer form an arrayed nanochannel structure between a source electrode and a drain electrode. The first arrayed pattern edge is interdigitated with an end of the arrayed nanochannel structure. The second arrayed pattern edge is interdigitated with another end of the arrayed nanochannel structure.

A semiconductor structure includes a first semiconductor layer, a second semiconductor layer, multiple third semiconductor structures, a conductive layer, and an insulating layer. The first semiconductor layer is disposed over a substrate. The second semiconductor layer is disposed on the first semiconductor layer. The third semiconductor structures are disposed on the second semiconductor layer. The conductive layer is disposed over the third semiconductor structures. The insulating layer is disposed between the conductive layer and the third semiconductor structures to electrically isolate the conductive layer from the third semiconductor structures. A two-dimensional electron gas channel is formed in a portion of the first semiconductor layer, the portion of the first semiconductor layer is not overlapped with the third semiconductor structures in a vertical direction, and the two-dimensional electron gas channel is located near an interface between the first semiconductor layer and the second semiconductor layer.