An organic light emitting diode display device are provided. The organic light emitting diode display device includes: a substrate; a barrier layer, located on a side of the substrate; a first buffer layer, located on a side of the barrier layer; a first semiconductor layer, located on a side of the first buffer layer; a first gate insulating layer, located on a side of the first semiconductor layer; a first gate electrode, located on a side of the first gate insulating layer; a second buffer layer, located on a side of the first gate electrode; a second semiconductor layer, located on a side of the second buffer layer; a second gate insulating layer, located on a side of the second semiconductor layer; a second gate electrode, located on a side of the second gate insulating layer.

A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.

Provided are a thin-film transistor substrate, a manufacturing method thereof, and a display apparatus. The thin-film transistor substrate includes: a substrate; a buffer layer on the substrate; a semiconductor layer arranged on the buffer layer and including a first conductive area, a second conductive area, and a channel area between the first conductive area and the second conductive area; a first dopant doped in an upper portion of the channel area at a first concentration; a second dopant doped in a lower portion of the channel area at a second concentration and being of a different type from a type of the first dopant; a gate insulating layer covering the semiconductor layer; and a gate electrode overlapping the channel area in a plan view and disposed on the gate insulating layer.

The present disclosure relates to a vertical gate-all-around thin film transistor and a method of manufacturing a vertical gate-all-around thin film transistor. The vertical gate-all-around thin film transistor includes a substrate; an isolation layer on the substrate; a source layer on the isolation layer; an annular thin film channel on the source layer; a drain layer on an upper part of the annular thin film channel; and a vertical surrounding gate filled on an inner side of the annular thin film channel and covering a sidewall of the annular thin film channel, wherein the substrate, the isolation layer, the source layer, the annular thin film channel, the drain layer, and the vertical surrounding gate are stacked sequentially from bottom to up.

Disclosed herein are a thin-film transistor and a preparation method therefor, and a memory and a display. The thin-film transistor comprises a first source/drain layer (1); a second source/drain layer (3); an insulating layer (2), which is located between the first source/drain layer (1) and the second source/drain layer (3); a channel layer (4), which is embedded in the first source/drain layer (1) and the insulating layer (2); and a gate electrode (5), which is embedded in the channel layer (4), wherein an embedded end of the channel layer (4) is in contact with the second source/drain layer (3), and a top end of the channel layer (4) and a top end of the gate electrode (5) are both flush with the first source/drain layer (1). The thin-film transistor provided in the present disclosure is a CAA architecture in which an annular channel is arranged surrounding the gate electrode (5), such that the performance of the transistor can be improved, and the power consumption can be reduced; moreover, there is no gate electrode (5) in the horizontal direction covering the first source/drain layer (1), such that the parasitic capacitance and current leakage of the gate electrode can be reduced.

A display apparatus can include a first thin film transistor including a first active layer including polycrystalline silicon, a first gate electrode overlapping the first active layer with a first gate insulation layer therebetween, and a first source electrode and a first drain electrode connected to the first active layer, a first interlayer insulation layer disposed on the first gate electrode, a second thin film transistor including a second active layer including an oxide semiconductor, a second gate electrode overlapping the second active layer with a second gate insulation layer therebetween, and a second source electrode and a second drain electrode connected to the second active layer, and a second interlayer insulation layer disposed on the first gate electrode, the second gate electrode, and the second gate insulation layer. Also, the second gate insulation layer and the second interlayer insulation layer comprise a dopant for doping the second active layer.

The present disclosure provides a semiconductor device, a method and an electronic apparatus. The semiconductor device includes a substrate; a channel layer stacking portion including multiple channel layers, a length direction of the channel layer is perpendicular to the thickness direction of the substrate, and the channel layer includes a first end, a middle section and a second end in the length direction; a gate-all-around surrounding the middle section; a source/drain functional portion; and a first spacer between the source/drain functional portion and the gate-all-around, between the first ends of adjacent channel layers and between the second ends of the adjacent channel layers. The first spacer includes first and second portions in the length direction, the first portion is in contact with the gate-all-around, the second portion is in contact with the source/drain functional portion. A material of the first portion is different from that of the second portion.

A transistor having a minute size is provided. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulating layer is provided over the first conductive layer and includes an opening reaching the first conductive layer and a depressed portion surrounding the opening in a plan view. The second conductive layer is provided to cover the inner wall of the depressed portion and includes a region facing the semiconductor layer with the first insulating layer therebetween. The semiconductor layer is provided to include a region overlapping with the opening and is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer. The second insulating layer is provided in contact with the top surface of the semiconductor layer. The third conductive layer is provided over the second insulating layer to cover the inner wall of the opening and includes a region facing the semiconductor layer with the second insulating layer therebetween.

A transistor including: a gate electrode; a semiconductor layer overlapping the gate electrode; a source electrode and a drain electrode overlapping a portion of the semiconductor layer, respectively, wherein a channel region of the semiconductor layer includes a first region and a third region, and a second region disposed between the first region and the third region, and a number of M-O bonds in the first region is different from a number of M-O bonds in the second region, wherein the M is a metal and the O is oxygen.

An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.