One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a first carrier nanosheet at least partially surrounded by a first 2D material and a second carrier nanosheet at least partially surrounded by a second 2D material. The transistor can include a first source/drain structure in electrical contact with a first end of the first 2D material and a first end of the second 2D material. The transistor can include a second source/drain structure in electrical contact with a second end of the first 2D material and a second end of the second 2D material. The transistor can include a gate structure at least partially surrounding the first 2D material and the second 2D material.

The present invention broadly relates to the fabrication and processing of graphene electronic devices on silicon which comprise a silicon dioxide passivation layer.

The present disclosure relates to vertical field effect transistors (FET). The vertical FET according to the invention includes a substrate and a first electrode configured as either a source or a drain of the transistor. The device includes a second electrode) configured as the other of the source and the drain, where the second electrode at least partially overlaps the first electrode in an overlapping region. Moreover, the device comprises an active layer that is sandwiched between the first electrode and the second electrode and a gate arrangement including a gate conductor portion and a gate insulating layer, which is arranged between the active layer and a gate conductor portion as to prevent direct contact between the active layer and the gate conductor portion. The active layer comprises a 1D material arranged with its longitudinal axis parallel to the substrate and/or a 2D material arranged with its plane substantially parallel to the substrate. The present disclosure further comprises a method for the manufacture of such vertical field effect transistors as well as for the manufacture of complementary logic devices.

As a field effect transistor (FET) having a transition metal dichalcogenide capped with a hydrocarbon (HC) protective film according to a preferred embodiment as a channel layer forms a dielectric thin film having a large area of a centimeter scale as a protective film on the surface of the transition metal dichalcogenide, the problem of lowering the electrical performance of the field effect transistor, which is generated due to scattering or trapping of carriers within the channel as impurity molecules such as oxygen, moisture, and the like existing in the surrounding environment are adsorbed on the surface of the transition metal dichalcogenide and act as defects, can be solved, and stability of long-term storage can be improved.

An ultrafast two-dimensional (2D) flash memory device based on Fowler-Nordheim (FN) tunneling, including a substrate, a gate electrode, a blocking layer, a floating gate, a tunneling layer, a 2D channel, a source electrode and a drain electrode. The gate electrode is provided at a middle of the substrate. The blocking layer is configured to cover the gate electrode and the substrate. The floating gate is provided on the blocking layer, and is entirely encompassed within a coverage area of the gate electrode. The tunneling layer is configured to cover the floating gate and the blocking layer. The 2D channel is provided on the tunneling layer, and is entirely encompassed within a coverage area of the floating gate. The source electrode and the drain electrode are configured to partially overlap with the 2D channel. A method for preparing such device is also provided.

A memory chip based on two-dimensional (2D) flash memories with complementary metal oxide semiconductor (CMOS) technology, including a substrate structure with a memory peripheral circuit and a 2D material flash memory array. The substrate structure is fabricated using CMOS technology, and the flash memory array is constructed from 2D material-based flash memories. The substrate is prepared by a standard CMOS process and includes different doping types of silicon on the substrate, metal wires for interconnections between devices, and dielectric layers for isolation. The flash memory array has a multi-layer structure.

A two-dimensional semiconductor material-based charge super-injection memory, including a substrate, a gate electrode, a blocking layer, a charge-trapping layer, a tunneling layer, a two-dimensional semiconductor channel layer, a drain electrode and a source electrode. The gate electrode is provided above the substrate. The blocking layer is configured to cover the gate electrode and the substrate. The charge-trapping layer is provided on the blocking layer. The tunneling layer is provided on the charge-trapping layer. The two-dimensional semiconductor channel layer is provided on the tunneling layer. The two-dimensional semiconductor channel layer is entirely encompassed within a coverage area of the gate electrode and a coverage area of the tunneling layer. The drain electrode and the source electrode are each partially overlapped with the two-dimensional semiconductor channel layer. A fabrication method of such charge super-injection memory is also provided.

Various embodiments may provide a transistor. The transistor may include a substrate, a first contact electrode and a second contact electrode over the substrate. The transistor may additionally include a two-dimensional semiconductor material layer above the substrate such that the first contact electrode is in contact with a first portion and the second contact electrode is in contact with a second portion of the two-dimensional semiconductor material layer. The transistor may further include a first control gate and a second control gate. The transistor may additionally include a main gate over a third portion of the two-dimensional semiconductor material layer, the third portion between the first portion and the second portion. The transistor may also include a dielectric layer separating the main gate, the first control gate and the second control gate from the two-dimensional semiconductor material layer.

A method for forming a 2D channel field-effect transistor device is provided. The method includes forming a device layer stack on a substrate. The device layer stack includes lower and upper sacrificial layers and a channel layer of a 2D material. The method further includes embedding the device layer stack in a dummy layer, forming a gate cavity in the dummy layer, and removing the sacrificial layers from the device layer stack by etching the sacrificial material from the gate cavity. After removing the sacrificial layers, the method includes forming an oxide liner along sidewalls of the gate cavity including an oxidation process to oxidize a thickness portion of the dummy layer, forming a gate stack in the gate cavity to surround the channel layer, forming source/drain contact cavities in the dummy layer, forming source/drain contacts in the source/drain contact cavities, and replacing the dummy layer with a dielectric layer.

A semiconductor device may include a channel layer including a two-dimensional material layer and a molecular crystal layer on the two-dimensional material layer, the two-dimensional material layer including a two-dimensional semiconductor material; a source electrode and a drain electrode, which respectively may be on both sides of the channel layer; and a gate insulating layer and a gate electrode, which respectively may be on the channel layer between the source electrode and the drain electrode. The molecular crystal layer may include a plate-shaped aromatic compound of C.sub.20-C.sub.40, and may have a thickness of 1 molecular layer to 5 molecular layers.