Provided herein is a method including forming a cavity in a first side of a first silicon wafer. An oxide layer is formed on the first side and in the cavity. The first side of the first silicon wafer is bonded to a first side of a second silicon wafer, and a gap control structure is deposited on a second side of the second silicon wafer. A MEMS structure is formed in the second silicon wafer. The second side of the second silicon wafer is eutecticly bonded to the third silicon wafer, and the eutectic bonding includes pressing the second silicon wafer to the third silicon wafer.

A semiconductor structure includes a first substrate including a cavity extended into the first substrate, a device disposed within the cavity, a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer, and a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer, wherein the first conductive structure is bonded with the second conductive structure and the first dielectric layer is bonded with the second dielectric layer to seal the cavity.

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

In described examples, a transient liquid phase (TLP) metal bonding material includes a first substrate and a base metal layer. The base metal layer is disposed over at least a portion of the first substrate. The base metal has a surface roughness (Ra) of between about 0.001 to 500 nm. Also, the TLP metal bonding material includes a first terminal metal layer that forms an external surface of the TLP metal bonding material. A metal fuse layer is positioned between the base metal layer and the first terminal metal layer. The TLP metal bonding material is stable at room temperature for at least a predetermined period of time.

Provided herein is a method including bonding a first oxide layer on a handle substrate to a second oxide layer on a complementary metal oxide semiconductor (“CMOS”), wherein the fusion bonding forms a unified oxide layer including a diaphragm overlying a cavity on the CMOS. The handle substrate is removed leaving the unified oxide layer. A piezoelectric film stack is deposited over the unified oxide layer. Vias are formed in the piezoelectric film stack and the unified oxide layer. An electrical contact layer is deposited, wherein the electrical contact layer electrically connects the piezoelectric film stack to an electrode on the CMOS.

MEMS devices and methods for forming the same are provided. A first metal interconnect structure is formed on a first semiconductor substrate to connect to a CMOS control circuit in the first semiconductor substrate. A bonding layer having a cavity is formed on the first metal interconnect structure, and then bonded with a second semiconductor substrate. A conductive plug passes through a first region of the second semiconductor substrate, through the bonding layer, and on the first metal interconnect structure. A second metal interconnect structure includes a first end formed on the first region of the second semiconductor substrate, and a second end connected to the conductive plug. Through-holes are disposed through a second region of the second semiconductor substrate and through a top portion of the bonded layer that is on the cavity to leave a movable electrode to form the MEMS device.

The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

A method for fusion bonding a pair of substrates together with silane preconditioning is provided. A surface of a first oxide layer or a surface of a second oxide layer is preconditioned with silane. The first and second oxide layers are respectively arranged on first and second semiconductor substrates. Water is applied to the surface of the first or second oxide layer. The surfaces of the first and second oxide layers are brought in direct contact. The first and second oxide layers are annealed. A method for manufacturing a microelectromechanical systems (MEMS) package using the fusion bonding is also provided.

An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.

A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.