A package structure and a manufacturing method thereof are disclosed. The structure includes at least one semiconductor die, a redistribution layer disposed on the at least one semiconductor die, and connectors there-between. The connectors are disposed between the at least one semiconductor die and the redistribution layer, and electrically connect the at least one semiconductor die and the redistribution layer. The redistribution layer includes a dielectric layer with an opening and a metallic pattern layer disposed on the dielectric layer, and the metallic pattern layer includes a metallic via located inside the opening with a dielectric spacer surrounding the metallic via and located between the metallic via and the opening.

Methods, systems, and devices for selective cavity merging for isolation regions in a memory die are described. For example, formation of material structures of a memory die may include depositing a stack of alternating layers of a first material and a second material over a substrate of the memory die, forming a pattern of cavities through the stack of alternating material layers, and forming voids between layers of the first material based on removing portions of the second material. An electrical isolation region may be formed between portions of the memory die based on depositing a dielectric material in at least some of the cavities and in at least a portion of the voids between the layers of the first material.

A transistor structure and a manufacturing method thereof are provided. The transistor structure includes a gate, doped regions and a gate dielectric structure. The gate is disposed on a substrate and includes a first portion and a second portion, wherein the second portion surrounds the first portion, and a material of the first portion is different from a material of the second portion. The doped regions are disposed in the substrate on both sides of the gate. The gate dielectric structure is disposed between the gate and the substrate.

A high-voltage transistor may include a composite gate dielectric layer having multiple regions with different dielectric constant values and/or a composite gate structure having multiple regions of different work function values. The composite dielectric layer having multiple regions with different dielectric constant values and/or the composite gate structure having multiple regions with different work functions increases the threshold voltage uniformity across a channel region of the high-voltage transistor. The increased threshold voltage uniformity may enable a low subthreshold swing and a low subthreshold off-stage current leakage to be achieved for the high-voltage transistor, which increases the operating efficiency of the high-voltage transistor and enables the size of the high-voltage transistor to be reduced without increasing (or with minimal increase to) the subthreshold swing and and/or the subthreshold off-stage current leakage of the high-voltage transistor.

A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

A semiconductor device includes a plurality of first resistor elements, an insulating layer and a plurality of second resistor elements. The plurality of first resistor elements are disposed at a side of a main surface of a semiconductor substrate, extending in a first direction parallel to the main surface of the semiconductor substrate, arranged in a second direction parallel to the main surface of the semiconductor substrate and intersecting with the first direction. The insulating layer is disposed at the side of the main surface of the semiconductor substrate between the respective plurality of first resistor elements and having an electrode installation surface in contact with the electrode layer. The plurality of second resistor elements are disposed on the electrode installation surface of the insulating layer between the plurality of first resistor elements, extending in the first direction, arranged in the second direction.

For manufacturing a memory device, a system may form a trench between a first portion and a second portion of a stack. A bottom wall of the trench may include a spacer material. The system may remove a first and a second oxide material to reform the trench, and remove a polysilicon material in a lateral direction to expose a third oxide material and a channel structure. The third oxide material may form the bottom wall of the trench. The system may remove, in a lateral direction, the first oxide material, a portion of the second oxide material, the third oxide material, and a fourth oxide material of the channel structure. The system may deposit a metal material, in the trench, in contact with a doped polysilicon material of the channel structure.

The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature.

The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature.

A method of manufacturing a semiconductor structure is disclosed. The semiconductor structure includes a transistor area, which includes a first source-drain area and a word line region. The method includes forming an active layer on a substrate, and the active layer of the transistor region includes a plurality of active structures. A dummy word line structure covering the active structure of the same layer is formed in the first source drain region and the word line region. The first isolation layers arranged alternately with the dummy word line structures in the third direction are formed. Then the dummy word line structure is removed. An initial dielectric layer is formed on the surface of the active structure of the first source-drain region and the word line region. An initial word line is formed on the surface of the initial dielectric layer. The initial word line and the initial dielectric layer located in the first source and drain region are removed.