H10W72/352

METHOD OF MAKING AN INVERTER

A method of making an inverter comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

BONDED STRUCTURE, SEMICONDUCTOR DEVICE, AND BONDING METHOD
20260076248 · 2026-03-12 ·

A bonding structure includes a first member and a second member. The first member includes a first layer mainly composed of a first metal. The second member includes a second layer mainly composed of a second metal different from the first metal. In the bonding structure, the first layer of the first member and the second layer of the second member are solid-phase bonded. As an example, the first metal is Cu, and the second metal is Ag. As another example, the first metal is Cu, and the second metal is Au. As a still another example, the first metal is Au, and the second metal is Ag.

Anionic Curable Compositions
20260071104 · 2026-03-12 ·

The present invention provides compositions, including die attach adhesives, coatings and underfill materials, which are useful in electronics packaging and the composite fields. Specifically, the invention provides liquid and very low melting epoxy-maleimide compositions that co-cure upon the addition of an anionic cure catalyst in the absence of any other cure catalyst.

METHOD FOR MANUFACTURING SINTER BONDING FILM, AND METHOD FOR MANUFACTURING POWER SEMICONDUCTOR PACKAGE

A method for manufacturing sinter bonding film, includes: preparing a resin formulation; preparing a metal filler mixture; mixing the resin formulation and the metal filler mixture, thereby preparing a paste for film manufacturing; and manufacturing a sinter bonding film by using the paste for film manufacturing. The metal filler mixture includes a metal powder and a reducing agent, copper metal (Cu) corresponds to respective particles in the metal powder, and the surface of the respective particles in the metal powder undergoes acid treatment or non-treatment.

SEMICONDUCTOR PACKAGE
20260083002 · 2026-03-19 · ·

A semiconductor package may include a package substrate, an interposer on the package substrate, photonics modules in the interposer and configured to perform communication based on optical signals, and a semiconductor chip on the interposer. A core substrate of the interposer may include through electrodes and cavities, where the through electrodes may extend from an upper surface of the core substrate to a lower surface of the core substrate. The cavities may extend from the upper surface of the core substrate to an inner portion of the core substrate where the through electrodes are not disposed. One of the photonics modules may be in each of the cavities. Each photonics module may include a photonics integrated circuit chip, and an electronic integrated circuit chip and an optical transmissive layer on an upper surface of the photonics integrated circuit chip.

Heat Dissipating Lid, Chip Package Structure, and Electronic Device

A heat dissipating lid includes a first surface configured to be connected to the chip, and a groove located on the first surface. The first surface includes a first contact region. In a chip package structure, a boundary of an orthographic projection of the chip on the first surface coincides with a boundary of the first contact region. The groove is located outside the first contact region and connected to the first contact region, and the groove extends along at least a portion of the boundary of the first contact region. The heat dissipating lid is applicable to the chip package structure and configured to dissipate heat for the chip.

Metal nitride core-shell particle die-attach material
12588521 · 2026-03-24 · ·

Die attach materials are provided. In one example, the die-attach material includes a plurality of core-shell particles. Each core-shell particle includes a core and a shell on the core. The core includes a conducting material. The shell includes a metal nitride.

Stacked semiconductor method and apparatus

A manufacturing method of a chip package, performing a coupling of first and second interconnecting layers between one or more top dies and one or more bottom dies via hybrid copper bonding; depositing a material to at least partially cover the second interconnecting layer; thinning a second surface of the one or more top dies, wherein both the one or more top dies and the material define a continuous surface; coupling a first surface of a support die to the second surface of at least one of the one or more top dies; thinning a second surface of at least one of the one or more bottom dies; and coupling the second surface of at least one of the one or more bottom dies to a plurality of microbumps.

Electronic device and method for manufacturing electronic device
12588520 · 2026-03-24 · ·

An electronic device which can suppress peeling off and damaging of the bonding material is provided. The electronic device includes an electronic component, a mounting portion, and a bonding material. The electronic component has an element front surface and an element back surface separated in the z-direction. The mounting portion has a mounting surface opposed to the element back surface on which the electronic component is mounted. The bonding material bonds the electronic component to the mounting portion. The bonding material includes a base portion and a fillet portion. The base portion is held between the electronic component and the mounting portion in the z-direction. The fillet portion is connected to the base portion and is formed outside the electronic component when seen in the z-direction. The electronic component includes two element lateral surface and ridges. The ridges are intersections of the two element lateral surface and extend in the z-direction. The fillet portion includes a ridge cover portion which covers at least a part of the ridges.

CHIP PACKAGING STRUCTURE AND PREPARATION METHOD

A chip packaging structure includes, a chip on a substrate; an enclosure structure on the chip, a wall of the enclosure structure comprises a sealed cavity, and the chip is revealed through the sealed cavity; a layer of thermal interface material for the chip, formed by filling a liquid metal into the sealed cavity of the wall of the enclosure structure; and a heat sink, formed on the layer of thermal interface material, is hermetically sealed to the wall of the enclosure structure. The heat sink component is formed on the layer of the thermal interface material, sealed and connected to the enclosure structure. The enclosure structure using flexible materials to prevent the liquid metal from overflowing in the encapsulation and application process, thereby reducing degradation. The UV curing adhesive is used for sealing and fixing the connection to the thermal interface material layer, so the disassembly and replacement of the process is simpler.