A microelectronic device includes a control logic structure including a high-power component. The microelectronic device also includes a memory array structure vertically offset from and attached to the control logic structure, the memory array structure comprising an array of memory cells. The microelectronic device further includes a heat sink structure vertically underlying and horizontally overlapping the high-power component, the heat sink structure comprising a material having higher thermal conductivity than semiconductor material of the control logic structure.

A semiconductor device includes a first semiconductor structure having a memory region, and a second semiconductor structure vertically overlapping the first semiconductor structure, the second semiconductor structure having a peripheral circuit region vertically overlapping the memory region. The first semiconductor structure includes a memory structure including a vertical channel transistor disposed in the memory region and an information storage structure disposed on the vertical channel transistor, and a cell routing line structure electrically connected to the memory structure. The second semiconductor structure includes a peripheral circuit disposed in the peripheral circuit region, and a peripheral routing line structure electrically connecting the peripheral circuit and the cell routing line structure to each other. The first semiconductor structure further includes a cell hydrogen supply layer disposed between the memory structure and the second semiconductor structure.

System-in-packages (SiPs) having vertically integrated processing units and combined high-bandwidth memory (HBM) devices, and associated devices and methods, are disclosed herein. In some embodiments, the SiP includes a processing unit and a HBM device carried by the processing unit. Further, the combined HBM device can include one or more volatile memory dies and one or more non-volatile memory dies. The SiP can also include a shared through silicon via (TSV) bus that electrically couples combined HBM device can also include a shared bus that is electrically coupled to each of the processing unit, the one or more volatile memory dies, and the one or more non-volatile memory dies to establish communication paths therebetween.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

Provided are a semiconductor chip, a semiconductor package including the same, and a method for manufacturing the same. This semiconductor chip includes a first logic die, first memory dies arranged side by side in a first direction on the first logic die, and a first mold layer between the first memory dies. The first memory dies and the first mold layer are in contact with an upper surface of the first logic die, each of the first memory dies includes first memory bank regions arranged side by side in a second direction intersecting the first direction, and the first logic die includes first core regions overlapping the first memory bank regions, respectively, in a third direction that is perpendicular to the first and second directions.

Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a memory array and a peripheral circuit coupled to the memory array. The peripheral circuit may be configured to, during a program phase of a first program loop, apply a first program voltage to a first word line and apply a second program voltage to a second word line adjacent to the first word line. An absolute value of a difference between the first program voltage and the second program voltage may be less than a first preset value. The peripheral circuit may be configured to, during the program phase of the first program loop, apply a first pass voltage to a third word line. The first pass voltage may be less than the first program voltage, and the first pass voltage may be less than the second program voltage.

A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.

Aspects of the disclosure provide a semiconductor device and a method to fabricate the semiconductor device. The semiconductor device includes a first die comprising a first contact structure formed on a face side of the first die. The semiconductor device includes a first semiconductor structure and a first pad structure that are disposed on a back side of the first die. The first semiconductor structure is conductively connected with the first contact structure from the back side of the first die and the first pad structure is conductively coupled with the first semiconductor structure. An end of the first contact structure protrudes into the first semiconductor structure without connecting to the first pad structure. The first die and a second die can be bonded face-to-face.

A three-dimensional integrated circuit (3D IC) including a first die, a second die, a bonding layer between the first and second dies. The bonding layer bonds the first and second dies. The 3D IC also includes a chipping and delamination barrier (CDB) extending across the first die, the bonding layer, and the second die.