A method of manufacturing a high electron mobility transistor (HEMT) structure is disclosed. By controlling a passivation layer and a barrier layer to uninterruptedly grow in the same growth chamber, defects of the passivation layer generated in the growth process due to a drastic change in temperature, pressure, or atmosphere or degrading a quality of an interface between the passivation layer and the barrier layer could be avoided, thereby providing the passivation layer with a good quality and the interface between the passivation layer and the barrier layer with a good quality, so that the objective of improving the performance of the HEMT structure could be achieved.

Semiconductor devices with die overthinning detection circuitry (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a semiconductor die includes a substrate, a triple well structure positioned at least partially within the substrate, and circuitry. The triple well structure can form a depletion region within the substrate, and the circuitry can be configured to capture a measurement of an amount of leakage current from the depletion region while a reverse bias is applied across the triple well structure. In some embodiments, the reverse bias can be applied across the triple well structure using part of a metallization die border of the semiconductor die. In these and other embodiments, measurement of the amount of leakage current can be used to detect that the semiconductor die is defective (e.g., overthinned, overpolished).

There is provided a technique that includes (a) receiving a recipe for measuring an object to be measured; (b) calculating an estimated time when measuring the object according to a setting order of respective measurement points set in the recipe; (c) changing the setting order of the respective measurement points set in the recipe according to a measurement pattern for measuring the object and calculating an estimated time when measuring the object according to the changed setting order; (d) selecting the setting order in which the estimated time is the shortest among the estimated times calculated in (b) and (c); and (e) measuring the object in the selected setting order.

A semiconductor wafer comprising a first die including a first integrated circuit having a trimmable or programmable component. The trimmable or programmable component is configured to be trimmed or permanently altered in response to an electrical signal. The semiconductor wafer also includes a saw street arranged adjacent to the first die, and at least one probe pad electrically connected to the trimmable or programmable component. The at least one probe pad is arranged in the saw street.

A semiconductor device manufacturing method including a reverse bias test for a device structure includes a step of applying a reverse bias voltage to the device structure, and a monitor step of monitoring a decrease rate of a leak current of the device structure at a time of applying the reverse bias voltage.

A film thickness measuring apparatus and an end point detector monitor a film thickness of a conductive film based on an output of an eddy current sensor disposed in a polishing table. The output of the eddy current sensor includes an impedance component, and when a resistance component and a reactance component of the impedance component are associated with the respective axes of a coordinate system having two orthogonal coordinate axes, at least some points on the coordinate system corresponding to the impedance component form at least a part of a circle. The film thickness measuring apparatus determines a distance between a point on the coordinate system and the center of the circle, determines the film thickness from the impedance component and corrects the determined film thickness using the determined distance.

A semiconductor device includes: a first semiconductor chip having an upper surface divided into a pixel array region and a connection region, wherein a plurality of pads are disposed in the connection region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the plurality of pads include: a first bonding pad for connection with an external circuit; and a first probing pad adjacent to the first bonding pad and for an electrical die sorting (EDS) test, and wherein the second semiconductor chip includes: a first space overlapping the first bonding pad in a vertical direction and in which at least a portion of an electrostatic discharge protection circuit is formed.

A method of manufacturing a semiconductor package includes manufacturing dies on each of wafers, testing the wafers including the dies, calculating total scores for the wafers according to results of the tests, and setting reference values corresponding to semiconductor products. The method also includes classifying, as the semiconductor product, a selected wafer having a total score corresponding to a selected reference value among the reference values. The method further includes packaging the dies included in the selected wafer.

An object is to provide a technique capable of reducing stress in the entire semiconductor device. The semiconductor device includes a plurality of sub-modules including a first sealing member, an insulating substrate provided with a first circuit pattern electrically connected to at least one of the conductive plates of the plurality of sub-modules, connection members electrically connected to at least one of the conductive pieces of the plurality of sub-modules, and a second sealing member having lower hardness than the first sealing member, which seals the plurality of sub-modules, the insulating substrate, and the connection members.

Described herein are manufacturing techniques and packages that enable wafer-scale heterogenous integration of electronic integrated circuits (EIC) with photonic integrated circuits (PIC) using a reconstitution-based fabrication approach. Wafer-scale photonic devices are formed by assembling strips of known-good dies (KGD). Such strips include arrays of adjacent reticles that have been singulated from a wafer. A strip can include a single row (or column) of reticles singulated from a wafer or multiple rows (or columns) that are adjacent to one another, enabling two-dimensional assembly and increased coverage. Wafer reconstitution involves transferring and bonding one or more strips of KGDs to a target substrate. A KGD is a reticle that is not part of an exclusion zone and has been verified to work properly. Thus, a reconstituted wafer includes strips that have verified to be fully functional.