A method for fabricating a semiconductor device, the method comprising the steps of: providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a groove exposing different crystal facing a planar surface; depositing a buffer layer over the substrate; epitaxially growing a semiconductor layer over the buffer layer, whereby least a portion of the buffer layer exhibits a cubic crystalline phase structure.

Porous III-nitrides having controlled/tuned optical, electrical, and thermal properties are described herein. Also disclosed are methods for preparing and using such porous III-nitrides.

A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and/or Cr.sub.2O.sub.3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

The invention relates to a method for obtaining a layer at least partially made of a nitride (N), first comprising the provision of a stack comprising at least one assembly of pads (1000A1-1000B4) extending from a substrate (100). Each pad comprises at least one creep section (220A1-220A5) and one crystalline section (300A1,300A5) surmounting the creep section (200A1-200A5). Then, a crystallite (510A1-510A5) is epitaxially grown on at least some of said pads until coalescence of the crystallites, so as to form a nitride layer (550A). The pads of the assembly are distributed over the substrate, such that the relative arrangement of the pads of the assembly is such that during the epitaxy of the crystallites, the progressive coalescence of the crystallites is always done between, on the one hand, a crystallite or a plurality of coalesced crystallites and, on the other hand, an isolated crystallite.

A method for manufacturing a group III nitride semiconductor substrate, that includes: growing a first AlN buffer layer on an Si substrate at a first growth temperature; growing a second AlN buffer layer on the first AlN buffer layer at a second growth temperature higher than the first growth temperature; and growing a group III nitride semiconductor layer on the second AlN buffer layer, wherein an Al raw material and an N raw material are alternately repeatedly fed in the growing the first AlN buffer layer.

A method for producing a power semiconductor device with heat dissipating capability includes epitaxially growing a GaN-based buffer layer on a first surface of a sapphire substrate, epitaxially growing a Ga.sub.2O.sub.3 semiconductor layer on the GaN-based buffer layer, forming a source and a drain, a gate dielectric layer, a first gate, an insulator layer, and a metal adhesive layer in sequence, removing part of the metal adhesive layer, the insulator layer, and the gate dielectric layer to expose one of the source and the drain, forming a heat sink which covers the metal adhesive layer, the insulator layer, the gate dielectric layer, and the one of the source and the drain, and conducting a laser lift-off process through a second surface of the sapphire substrate to remove the sapphire substrate and the GaN-based buffer layer.

A wafer includes a buried substrate; a layer of silicon (100) disposed on the buried substrate and forming multiple U-shaped grooves, wherein each U-shaped groove comprises a bottom portion and silicon sidewalls (111) at an angle to the buried substrate; a buffer layer disposed within the multiple U-shaped grooves; and multiple gallium nitride (GaN)-based structures having vertical sidewalls disposed within and protruding above the multiple U-shaped grooves, the multiple GaN-based structures each including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111).

The present invention is a nitride semiconductor wafer, including: a silicon single-crystal substrate; and a device layer composed of a nitride semiconductor above the silicon single-crystal substrate, wherein the silicon single-crystal substrate is a CZ silicon single-crystal substrate, and has a resistivity of 1000 .Math.cm or more, an oxygen concentration of 5.010.sup.16 atoms/cm.sup.3 (JEIDA) or more and 2.01.0.sup.17 atoms/cm.sup.3 (JEIDA) or less, and a nitrogen concentration of 5.010.sup.14 atoms/cm.sup.3 or more. This provides a nitride semiconductor wafer that hardly causes plastic deformation even using a high-resistant low-oxygen silicon single-crystal substrate produced by the CZ method, which is suitably used for a high-frequency device, and that can reduce warpage of the substrate.

A heterogeneous epitaxial structure formed on a SiC (silicon carbide) substrate. An intermediate layer comprising AIN is formed overlying the SiC substrate. The surface of the intermediate layer comprises AIN formed by lateral epitaxial growth. The lateral epitaxial growth merges to form the surface comprising a MELO layer (merged epitaxial lateral overgrowth). The intermediate layer includes a carbon layer underlying the MELO layer. At least one device layer comprising GaN (gallium nitride) is formed overlying the surface of the intermediate layer in which one or more semiconductor devices are formed. The carbon layer is heated to fracture portions of the intermediate layer to separate the SiC substrate from the intermediate layer. The SiC substrate is not consumed by the separation thereby allowing perpetual reuse in semiconductor wafer processing.

In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.