Provided is a semiconductor structure, a test structure, a manufacturing method and a test method. The semiconductor structure includes a substrate, which includes multiple pillars spaced along a first direction by first trenches; second trenches formed at opposite sides along a second direction of each of the pillars; target conductive structures extending along the second direction in the substrate directly below adjacent second trenches; and a first dielectric layer, a conductive layer and a second dielectric layer sequentially stacked in the first trenches and the second trenches. A depth of the first trenches is greater than that of the second trenches. The first direction intersects the second direction.

Integrated circuit structures including an interconnect feature without a higher-resistance liner material. In absence of a liner, metal of low resistance directly contacts an adjacent dielectric material, enabling lower resistance interconnect. Even for low-k dielectric compositions, adhesion of the metal to the dielectric material is improved through the incorporation of nitrogen proximal to the interface. Prior to deposition of the metal upon a surface of the dielectric, the surface is exposed to nitrogen species to form a nitrogen-rich compound at the surface. The metal deposited upon the surface may then be nitrogen-lean, for example a substantially pure elemental metal or metal alloy.

A method for forming floating gates in a non-volatile memory array is disclosed, comprising: patterning and etching portions of a hard-mask dielectric layer, a conductive layer and a tunneling oxide layer to define stacked structures over a substrate; conformally depositing a spacer dielectric layer over the substrate; etching a portion of the spacer dielectric layer to form spacers along sidewalls of each stacked structure; etching a portion of the substrate to form trenches so that the trenches and the stacked structures are alternately arranged in each row; and, growing liners on silicon walls of the trenches. Here, the hard-mask dielectric layer and the spacer dielectric layer comprise an oxidation-blocking material. Accordingly, the poly-silicon floating-gates are encapsulated in the hard-mask dielectric layer and the spacers such that the shapes of floating-gates and the tunneling oxide thickness are well preserved.

A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.

One or more dielectric inserts are formed in a through-substrate interconnect structure to prevent, minimize, and/or otherwise reduce the amount of dishing that occurs in the top surface of the through-substrate interconnect structure during planarization of the through-substrate interconnect structure. The dielectric insert(s) are formed of a dielectric material having a hardness that is greater than the hardness of the metal material of the through-substrate interconnect structure. The greater hardness enables the dielectric insert(s) to resist material removal during planarization of the through-substrate interconnect structure, which enables a high uniformity in the material removal rates across the top surface of the through-substrate interconnect structure to be achieved. The reduced amount of dishing during planarization of the through-substrate interconnect structure reduces the likelihood of removal of liner material from one or more liners between the sidewalls of the through-substrate interconnect structure and the substrate layer.

A semiconductor structure includes an SOI substrate having a base substrate, a buried oxide layer on the base substrate, and a device layer on the buried oxide layer, a circuit element disposed on the device layer and surrounded by a trench isolation region in the SOI substrate; an etch stop layer disposed around the circuit element; a first dielectric layer disposed on the etch stop layer; and a buried power rail embedded in the first dielectric layer, the etch stop layer, the trench isolation region, and the buried oxide layer. The buried power rail is isolated from the device layer through the buried oxide layer and trench-filling oxide in the trench isolation region.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first and a second transistor; a power rail via between the first and the second transistor; a backside via below the power rail via, the backside via having a first portion directly contacting the power rail via and a second portion underneath the first portion; and an isolation spacer surrounding the second portion of the backside via. The backside via further includes a third portion underneath the second portion. A backside capping layer underneath the isolation spacer surrounds the third portion of the backside via. A method of forming the same is also provided.

A semiconductor device includes a substrate, a gate trench in the substrate, a gate insulating film in the gate trench, a titanium nitride (TiN)-lower gate electrode film on the gate insulating film, the titanium nitride (TiN)-lower gate electrode film including a top surface, a first side surface, and a second side surface opposite the first side surface, a polysilicon-upper gate electrode film on the titanium nitride (TiN)-lower gate electrode film, and a gate capping film on the polysilicon-upper gate electrode film. A center portion of the top surface of the titanium nitride (TiN)-lower gate electrode film overlaps a center portion of the polysilicon-upper gate electrode film in a direction that is perpendicular to a top surface of the substrate, and each of the first side surface and the second side surface of the titanium nitride (TiN)-lower gate electrode film is connected to the gate insulating film.

An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization patterns therein, the metallization patterns including a top metal layer including top metal structures, forming a passivation layer over the top metal structures of the first interconnect structure, forming a first opening through the passivation layer, forming a probe pad in the first opening and over the passivation layer, the probe pad being electrically connected to the first top metal structure, performing a circuit probe test on the probe pad, removing the probe pad, and forming a bond pad and a bond via in dielectric layers over the passivation layer, the bond pad and bond via being electrically coupled to a second top metal structure of the top metal structures and a third top metal structure of the top metal structures.

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a word line structure including a word line dielectric layer in the substrate and including a U-shaped profile, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer including a U-shaped profile, between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; and a top capping layer covering the bottom capping layer and the word line structure. Top surfaces of the top thickening layer and the word line dielectric layer are coplanar and higher than the substrate.