A method for processing a wafer is provided. The method includes providing a wafer, in which the wafer has a first region and a second region, and the second region is between an edge of the wafer and the first region; depositing a first metallic layer on the wafer; depositing a cap layer on the first metallic layer; disposing a dielectric layer on the cap layer, in which the dielectric layer covers a sidewall of the first metallic layer and a sidewall of the cap layer; performing a polishing process to the dielectric layer, such that a consumed portion of the cap layer and a consumed portion of the first metallic layer is formed in the second region of the wafer.

A method of fabricating a pixel array substrate includes forming a semiconductor layer on a substrate, forming a metal layer stack on the semiconductor layer, forming a photoresist pattern on the metal layer stack, and removing part of the metal layer stack and the semiconductor layer not covered by the photoresist pattern at one time using a dry etching process to form a source, a drain, and a semiconductor pattern of an active device. The metal layer stack includes a first titanium layer, an aluminum layer, and a second titanium layer. The semiconductor pattern has a groove located between the source and the drain. The source and the drain respectively have a source edge and a drain edge opposite to each other, which defines two opposite side walls of the groove respectively. A pixel array substrate produced by using the method of fabricating the pixel array substrate is also disclosed.

A cleaning method according to one aspect of the present disclosure which cleans an electrostatic chuck includes exposing the electrostatic chuck to plasma and maintaining a relationship between a potential of the electrostatic chuck and a potential of the plasma such that electron current is introduced from the plasma toward the electrostatic chuck.

A substrate, a first layer disposed on the substrate, and a second layer disposed on the first layer are provided. An opening is etched through the second layer to the first layer. A first portion of the first layer is etched through the opening using a first etchant, to expose a surface of the substrate through the opening. A feature is deposited on the surface of the substrate through the opening. A second portion of the first layer is etched using a gaseous etchant, to release the substrate from the second layer.

The present disclosure discloses a method for manufacturing a via, including: forming a first dielectric layer on the surface of an underlying structure; performing patterned etching on the first dielectric layer to form a via opening; forming a first metal layer; performing first-time metal CMP to remove the first metal layer on the outer surface of the via opening, where a top surface of the first metal layer in the via opening is located below a top surface of the first dielectric layer; performing second-time dielectric etch back, to selectively etch the first dielectric layer, lower the top surface of the first dielectric layer as being below the top surface of the first metal layer, and form a metal protrusion of a via; and forming a pattern of an upper metal interconnection layer.

Embodiments of the disclosure include apparatus and methods for molybdenum nucleation layer formation. A molybdenum nucleation layer is formed on a metal layer disposed within a damascene structure formed in a surface of a substrate maintained at a processing temperature of less than 425 degrees Celsius. The damascene structure includes a plurality of vias and the metal layer is disposed at a bottom surface of the plurality of vias. To form the molybdenum nucleation layer, a molybdenum-containing precursor (MCP) is delivered to the substrate for a first period of time. A reactive precursor gas is delivered to the substrate for the first period of time. A carrier gas is delivered to the substrate for a second period of time. The reactive precursor gas is delivered to the substrate for a third period of time. A molybdenum layer is deposited within the plurality of vias on the molybdenum nucleation layer.

The present disclosure relates to methods and apparatuses for depositing metal-containing material on a substrate by a selective deposition process. The method comprises providing a substrate in a reaction chamber, providing a metal alkoxide precursor into the reaction chamber in a vapor phase; and providing a second precursor into the reaction chamber in a vapor phase to form metal-containing material on the substrate. The second precursor according to the disclosure comprises a borane compound and the substrate comprising a first surface and a second surface.

Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.

An MLG (multilayer graphene) device layer structure is connected with a via. The structure includes an M1 MLG interconnect device layer upon a dielectric layer. Interlayer dielectric isolates the M1 MLG interconnect device layer. An M2 MLG interconnect device layer is upon the interlayer dielectric. A metal via penetrates through the M2 MLG interconnect device layer, the interlayer dielectric and the M1 MLG interconnect device layer and makes edge contact throughout the thickness of both M1 MLG and M2 MLG layers. A method diffuses carbon from a solid phase graphene precursor through a catalyst layer to deposit MLG on a dielectric or metal layer via application of mechanical pressure at a diffusion temperature to form MLG layers.

A highly conductive and heat-dissipating chip and a manufacturing method thereof are provided. The manufacturing method includes: providing a substrate having a first surface and a second surface that is opposite to the first surface; forming a groove having at least one arc shape on the substrate; and filling a heat-dissipating material into the groove. Accordingly, a heat dissipation effect of the substrate can be enhanced, a structure of the substrate can be protected, and a service life of the substrate can be prolonged.