A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer, wherein the first semiconductor layer has a higher germanium concentration than the second semiconductor layer; forming a semiconductor cap over the second semiconductor layer; forming a first bonding layer over the semiconductor cap; bonding the first boding layer to a second bonding layer over a carrier substrate to form a bonded structure; and performing a wafer splitting process to split the first semiconductor layer into a first portion and a second portion separated from each other, such that the first portion of the first semiconductor layer and the substrate are removed from the bonded structure.

A method for transferring a thin layer onto a carrier substrate comprises preparing a carrier substrate using a preparation method involving supplying a base substrate having, on a main face, a charge-trapping layer and forming a dielectric layer having a thickness greater than 200 nm on the charge-trapping layer. Once the dielectric layer is formed, the ionized deposition and sputtering of the dielectric layer are simultaneously performed. The transfer method also comprises assembling, by way of molecular adhesion and with an unpolished free face of the dielectric layer, a donor substrate to the dielectric layer of the carrier substrate, the donor substrate having an embrittlement plane defining the thin layer. Finally, the method comprises splitting the donor substrate at the embrittlement plane to release the thin layer and to transfer it onto the carrier substrate.

A method for transferring a semiconductor layer from a donor substrate having a weakening plane to a receiver substrate having comprising a bonding face that has open cavities includes putting the donor substrate and the bonding face of the receiver substrate in contact, producing an assembly wherein the cavities are buried, and separating the assembly by fracture along the weakening plane. The bonding face of the receiver substrate includes, apart from the open cavities, a bonding surface that comes into contact with the donor substrate when the assembly is produced. The bonding surface includes a region devoid of cavities one dimension of which is at least 100 m and which has a surface area of at least 1 mm.sup.2, and an intercavity space that occupies from 15 to 50% of the bonding face of the receiver substrate.

A process for fabricating a semiconductor or piezoelectric structure comprises the following successive steps: (a) providing a donor substrate comprising a piezoelectric or semiconductor layer, (b) providing a receiver substrate, (c) treating a free surface of the donor substrate and/or a free surface of the receiver substrate, (d) bonding the donor substrate to the receiver substrate, the at least one treated free surface being at the interface between the donor substrate and the receiver substrate, and (e) transferring a portion of the piezoelectric or semiconductor layer from the donor substrate to the receiver substrate. The treatment of the free surface of the donor substrate and/or of the free surface of the receiver substrate comprises the following successive steps: (c1) chemical-mechanical polishing, and (c2) removing material from a peripheral region of the polished surface.

Cleaving systems and methods for cleaving a semiconductor structure. The systems and methods may involve a combination of thermally and mechanically induced stress. The cleave system may include a vacuum chuck which deflects the semiconductor structure and a heater which heats the structure while the vacuum is applied. The combination of thermal and mechanical stress causes the structure to cleave along a cleave plane.

The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 .Math.cm and 30 k.Math.cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer.

Fully-depleted silicon-on-insulator structures and methods for preparing fully-depleted silicon-on-insulator structures. The fully-depleted silicon-on-insulator structure may include a top layer, a handle structure and a dielectric layer disposed between the silicon top layer and handle structure. The dielectric layer of the silicon-on-insulator structure may be composed of hafnia, zirconia, alumina, or combinations thereof. In some embodiments, the dielectric layer is relatively thick such as at least 20 nm or even at least 50 nm.

A holding device for a fracturable assembly, which is intended to separate along a fracture plane defined between an upper part and a lower part of the fracturable assembly, comprises at least two protrusions configured to keep the fracturable assembly suspended in a substantially horizontal holding position, the protrusions being intended to be located between the upper part and the lower part, against a peripheral chamfer of the upper part; a support located below and at a distance from the protrusions so as to gravitationally receive the lower part when the fracturable assembly is separated, and to keep it at a distance from the upper part held by the protrusions.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.