The present application discloses a method for manufacturing a source/drain epitaxial layer of an FDSOI MOSFET, comprising: step 1, forming a shallow trench isolation on an FDSOI substrate; step 2, opening a formation region of a source/drain region of the MOSFET; step 3, performing first epitaxial growth to form a first pure silicon epitaxial layer; step 4, performing a first etching process to remove polysilicon particles generated from step 3; and step 5, performing epitaxial growth to sequentially form a second source/drain epitaxial seed layer, a third source/drain epitaxial bulk layer, and a fourth source/drain epitaxial cap layer on a surface of the first pure silicon epitaxial layer, so the four epitaxial layers are stacked to form the source/drain epitaxial layer.

A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ILD) layer on the active device; a first contact plug in the ILD layer and electrically connected to the active device; and a second contact plug in the ILD layer and the insulating layer, wherein a top surface of the second contact plug is higher than a top surface of the ILD layer.

The present disclosure relates to semiconductor structures and, more particularly, to a substrate with trap rich and low resistivity regions and methods of manufacture. The structure includes: a high resistivity semiconductor substrate; an active device over the high resistivity semiconductor substrate; and a low resistivity region floating in the high resistivity semiconductor substrate and which is below the active device.

A semiconductor device includes a semiconductor layer, a drift region formed in the semiconductor layer, and a dielectric film formed in the drift region. The drift region includes a first side well, a second side well and a well stack. The first side well has a first type conductivity. The second side well has the first type conductivity. The well stack is disposed laterally between the first side well and the second side well, and includes a plurality of intermediate wells that are stacked from top to bottom. A topmost one of the intermediate wells has a second type conductivity opposite to the first type conductivity, and covers bottom and side surfaces of the dielectric film. Two adjacent ones of the intermediate wells have different type conductivities.

A semiconductor device includes a substrate having an insulating layer and a device layer disposed on the insulating layer, wherein the device layer includes an active region, a plurality of gate structures arranged parallel to each other on the active region, a recess formed in the active region located between adjacent two of the gate structures and extending through the device layer, an epitaxial layer filling the recess, and an air gap between a bottom surface of the epitaxial layer and a top surface of the insulating layer.

A method for manufacturing a semiconductor structure includes: forming a trench in a semiconductor substrate; forming an isolating material layer on the semiconductor substrate and in the trench; forming a protective material layer on the isolating material layer and in the trench; removing horizontal portions of the protective material layer to form a protective layer laterally covering the isolating material layer and to expose horizontal portions of the isolating material layer from the protective layer; removing the horizontal portions of the isolating material layer to form an isolation layer that laterally covers the semiconductor substrate and that is disposed between the protective layer and the semiconductor substrate; and forming a conductive material layer to fill the trench.

A manufacturing method of a gate structure includes the following steps. A semiconductor substrate is provided. An isolation structure is formed in the semiconductor substrate and surrounds an active region in the semiconductor substrate. A gate pattern is formed on the active region and the isolation structure. The gate pattern includes a first gate structure and a first capping layer disposed on the first gate structure. A part of the first capping layer located above an interface between the active region and the isolation structure is removed for exposing a part of the first gate structure located above the interface between the active region and the isolation structure. A removing process is performed for reducing a thickness of the part of the first gate structure located above the interface between the active region and the isolation structure.

A semiconductor device includes an n-type buried layer, a first N-well region, a p-type body region, a first source/drain region, a second source/drain region, a gate structure, a second N-well region, and a first silicide region. The n-type buried layer in a substrate. The first N-well region is over the n-type buried layer. The p-type body region abuts the first N-well region. The first source/drain region is in the first N-well region. The second source/drain region is in the p-type body region. The gate structure extends across a boundary of the first N-well region and the p-type body region. The second N-well region is over the n-type buried layer. The first silicide region forms a Schottky contact with the second N-well region.

Disclosed semiconductor structures include a stack of III-V semiconductor layers and a III-V semiconductor device and a silicon device on the stack. The III-V semiconductor device includes, among other components, a barrier layer above and immediately adjacent to a III-V semiconductor surface at the top of the stack in a first area. The silicon device includes, among other components, a silicon-based layer above and immediately adjacent to the same III-V semiconductor surface at the top of the stack in a second area. Thus, the barrier layer and the silicon-based layer are at the same level above the substrate. Optionally, an isolation well can be within the stack adjacent to the III-V semiconductor surface in the second area (e.g., to electrically isolate the III-V semiconductor device from the silicon device). Also disclosed are methods of forming the semiconductor structures.

A semiconductor device is provided. A semiconductor device includes a first semiconductive region, a second semiconductive region, an isolation structure and at least one inner via. The isolation structure is formed between the first semiconductive region and the second semiconductive region and includes an isolation bottom formed beneath the second semiconductive region; and an isolation ring having a lower portion connecting the isolation bottom and an upper portion surrounding the second semiconductive region. The at least one inner via is formed in the second semiconductive region, on the isolation bottom and surrounded by the isolation structure. The isolation structure and the least one inner via have insulating materials.