A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.

A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.

A method of making a semiconductor device is provided. A monolithic die having at least two semiconductor dies is provided. Each of the at least two semiconductor dies includes a substrate and an epitaxial layer formed on the substrate. An isolation structure is formed electrically isolating two semiconductor dies of the at least two semiconductor dies. The isolation structure traverses the thickness of the substrate and the epitaxial layer and includes a first isolation trench.

A support substrate for a radiofrequency application comprises: a base substrate made of monocrystalline silicon comprising P-type dopants and having a resistivity that is greater than or equal to 250 ohm.Math.cm and strictly less than 500 ohm.Math.cm, and a content of interstitial oxygen between 13 ppma and 19 ppma, an epitaxial layer made of monocrystalline silicon comprising P-type dopants, disposed on the base substrate and having a thickness between 2 microns and 30 microns, an upper portion at least of the epitaxial layer having a resistivity greater than 3000 ohm.Math.cm, a charge-trapping layer made of polycrystalline silicon having a resistivity greater than or equal to 1000 ohm.Math.cm and a thickness between 1 micron and 10 microns. A method is used for manufacturing such a support substrate.

A structure includes a substrate having a frontside and a backside. A first electrode is in a first insulator layer and is adjacent to the frontside of the substrate. The first electrode is part of a redistribution layer (RDL). A second electrode is between the substrate and the first electrode. A dielectric-filled trench in the substrate is under the first electrode and the second electrode, the dielectric-filled trench may extend fully to the backside of the substrate. The structure provides a galvanic isolation that exhibits less parasitic capacitance to the substrate from the lower electrode.

A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.

A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

A semiconductor device structure and a formation method are provided. The method includes forming a sacrificial base layer over a substrate and forming a semiconductor stack over the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack to partially cover the sacrificial base layer, the semiconductor layers, and the sacrificial layers. The method further includes removing the sacrificial base layer to form a recess between the substrate and the semiconductor stack. In addition, the method includes forming a metal-containing dielectric structure to partially or completely fill the recess. The metal-containing dielectric structure has multiple sub-layers.

A wafer is processed by causing a cutting blade to cut into an outer circumferential surplus region of a first wafer from the front surface side by a predetermined thickness and executing cutting along the outer circumferential edge to form an annular step part in the outer circumferential surplus region, bonding the front surface side of the first wafer and the front surface side of a second wafer to form a bonded wafer, forming an annular modified layer by positioning the focal point of a laser beam with a wavelength having transmissibility with respect to the first wafer to the inside of the first wafer and executing irradiation with the laser beam along the boundary between a device region and the outer circumferential surplus region from the back surface side, and grinding the back surface side of the first wafer to execute thinning to a predetermined finished thickness.