The gate electrode of a transistor includes at least one region with a p-type work function and at least one region with an n-type work function. The regions are located over corners formed between isolation regions and an active region. The double hump effect is reduced, which provides higher operational frequencies.

A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, a source region and a drain region, and a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.

The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 .Math.cm and 30 k.Math.cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer.

A method for manufacturing a semiconductor structure includes the following operations. A base and a dielectric layer arranged on the base are provided. A first conductive pillar, a second conductive pillar and a third conductive pillar arranged in the dielectric layer are formed. A mask layer is formed. A portion of a thickness of the third conductive pillar is etched by using the third mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another, in which the third upper conductive pillar, the third lower conductive pillar and the dielectric layer are configured to form at least one groove. A cover layer filling the at least one groove is formed, in which the cover layer exposes the top surface of the third upper conductive pillar.

A method for manufacturing a semiconductor structure includes the following operations. A base and a dielectric layer arranged on the base are provided. A first conductive pillar, a second conductive pillar and a third conductive pillar arranged in the dielectric layer are formed. A mask layer is formed. A portion of a thickness of the third conductive pillar is etched by using the third mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another, in which the third upper conductive pillar, the third lower conductive pillar and the dielectric layer are configured to form at least one groove. A cover layer filling the at least one groove is formed, in which the cover layer exposes the top surface of the third upper conductive pillar.

An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter. .

Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes microwave annealing a dielectric bonding layer of a first element by exposing the dielectric bonding layer to microwave radiation and then directly bonding the dielectric bonding layer of the first element to a second element without an intervening adhesive. The bonding method also includes depositing the dielectric bonding layer on a semiconductor portion of the first element at a first temperature and microwave annealing the dielectric bonding layer at a second temperature lower than the first temperature.

A high voltage semiconductor device isolation structure and a method of manufacturing the same prevent a silicon penetration region from being formed between a first STI region and the side wall of a DTI region so that the breakdown voltage characteristic of a device is prevented from being decreased due to electric field concentration on the penetration region, and a method of manufacturing the same.

Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0 C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0 C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

Described examples include an integrated circuit that includes a trench extending into a semiconductor substrate. A silicon nitride body is located within the trench. A polysilicon electrode extends over the silicon nitride body, and a silicon oxynitride layer is located between the silicon nitride body and the polysilicon electrode.