An electrodeposition composition comprising: (a) a source of copper ions; (b) an acid; (c) a suppressor; and (d) a leveler, wherein the leveler comprises a quaternized dipyridyl compound prepared by reacting a dipyridyl compound with a difunctional alkylating agent or a quaternized poly(epihalohydrin). The electrodeposition composition can be used in a process for forming a copper feature over a semiconductor substrate in wafer level packaging to electrodeposit a copper bump or pillar on an underbump structure of a semiconductor assembly.

Electroplating systems may include an electroplating chamber. The systems may also include a replenish assembly fluidly coupled with the electroplating chamber. The replenish assembly may include a first compartment housing anode material. The first compartment may include a first compartment section in which the anode material is housed and a second compartment section separated from the first compartment section by a divider. The replenish assembly may include a second compartment fluidly coupled with the electroplating chamber and electrically coupled with the first compartment. The replenish assembly may also include a third compartment electrically coupled with the second compartment, the third compartment including an inert cathode.

An electroplating apparatus for electroplating metal on a substrate includes a plating chamber configured to contain an electrolyte, a substrate holder configured to hold and rotate the substrate during electroplating, an anode, and an azimuthally asymmetric auxiliary electrode configured to be biased both anodically and cathodically during electroplating. The azimuthally asymmetric auxiliary electrode (which may be, for example, C-shaped), can be used for controlling azimuthal uniformity of metal electrodeposition by donating and diverting ionic current at a selected azimuthal position. In another aspect, an electroplating apparatus for electroplating metal includes a plating chamber configured to contain an electrolyte, a substrate holder configured to hold and rotate the substrate during electroplating, an anode, a shield configured to shield current at the periphery of the substrate; and an azimuthally asymmetric auxiliary anode configured to donate current to the shielded periphery of the substrate at a selected azimuthal position on the substrate.

Electrochemical analysis method and system for monitoring and controlling the quality of electrochemical deposition and/or plating processes. The method uses a fingerprinting analysis method of an output signal to indicate whether the chemistry and/or process is operating in the normally expected range and utilizes one or more substrates as working electrode(s) and a) whereby the potential between the one or more working electrodes and one or more reference electrodes is analyzed to provide an output signal fingerprint which is represented as potential difference as a function of time or b) the input power of a process power supply to provide input energy in the form of current and/or potential between the working electrode(s) and a counter-electrode whereby the method utilizes the potential between the one or more working electrode(s) and at least one of: one or more reference electrodes; or one or more counter-electrodes; to provide an output signal fingerprint.

Electrochemical analysis method and system for monitoring and controlling the quality of electrochemical deposition and/or plating processes. The method uses a fingerprinting analysis method of an output signal to indicate whether the chemistry and/or process is operating in the normally expected range and utilizes one or more substrates as working electrode(s) and a) whereby the potential between the one or more working electrodes and one or more reference electrodes is analyzed to provide an output signal fingerprint which is represented as potential difference as a function of time or b) the input power of a process power supply to provide input energy in the form of current and/or potential between the working electrode(s) and a counter-electrode whereby the method utilizes the potential between the one or more working electrode(s) and at least one of: one or more reference electrodes; or one or more counter-electrodes; to provide an output signal fingerprint.

A plating method for plating a substrate by increasing a current value from a predetermined current value to a first current value is provided. The plating method plates the substrate for a first predetermined period with the first current value when a first current density corresponding to the first current value is lower than a limiting current density. This plating method includes measuring a voltage value applied to the substrate, and when the current value is increased from the predetermined current value to the first current value, determining whether the first current density is equal to or more than the limiting current density or not based on an amount of change in the voltage value.

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.

An interconnect structure of a semiconductor device includes a conductive via and a barrier layer lining an interface between a dielectric layer and the conductive via. The barrier layer is selectively deposited along sidewalls of a recess formed in a dielectric layer. The conductive via is formed by selectively electroplating electrically conductive material such as rhodium, iridium, or platinum in an opening of the recess, where the conductive via is grown upwards from an exposed metal surface at a bottom of the recess. The conductive via includes an electrically conductive material having a low electron mean free path, low electrical resistivity, and high melting point. The interconnect structure of the semiconductor device has reduced via resistance and improved resistance to electromigration and/or stress migration.

A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.

A bonding structure formed on a substrate includes an indium layer and a passivating nickel plating formed on the indium layer. The nickel plating serves to prevent a reaction involving the indium layer.