According to an example aspect of the present invention, there is provided a wafer level package for a device, the package comprising: a first substrate and a second substrate, a sealing structure comprising a seal ring and a bonding layer between the first substrate and the second substrate, and a lateral electrical connection line on a surface of the first substrate, which lateral electrical connection line extends through the seal ring for creating an electrical connection between the device inside the package and an electrical circuit outside the package.

The present invention provides a MEMS pressure sensor and a manufacturing method. The pressure is formed by a top cap wafer, a MEMS wafer and a bottom cap wafer. The MEMS wafer comprises a frame and a membrane, the frame defining a cavity. The membrane is suspended by the frame over the cavity. The bottom cap wafer closes the cavity. The top cap wafer has a recess defining with the membrane a capacitance gap. The top cap wafer comprises a top cap electrode located over the membrane and forming, together with the membrane, a capacitor to detect a deflection of the membrane. Electrical contacts on the top cap wafer are connected to the top cap electrode. A vent extends from outside of the sensor into the cavity or the capacitance gap. The pressure sensor can include two cavities and two capacitance gaps to form a differential pressure sensor.

The present disclosure relates to an integrated package having an active area, an electrical routing circuit, an optical routing circuit, and a vacuum vessel. Methods of making such a package are also described herein.

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

A three dimensional (3D) micro-electro-mechanical system (MEMS) device is provided. The device comprises a central MEMS wafer, and top and bottom cap wafers. The MEMS wafer includes a MEMS structure, such as an inertial sensor. The 5 top cap wafer, the bottom cap wafer and the MEMS wafers are stacked along a stacking axis and together form at least one hermetic cavity enclosing the MEMS structure. At least one of the top cap wafer and the bottom cap wafer is a silicon-on- insulator (SOI) cap wafer comprising a cap device layer, a cap handle layer and a cap insulating layer interposed between the cap device layer and the cap handle layer. At 10 least one electrically conductive path extends through the SOI cap wafer, establishing an electrical convection between an outer electrical contact provided on the SOI cap wafer and the MEMS structure.

A MEMS sensor device package comprises a sensor assembly comprising a sensor device and a sensor circuit communicating coupled to the sensor device, The MEMS sensor device package further comprises an assembly package housing having a top member and a bottom member attached to the top member for encapsulating the sensor assembly. A passageway fluidly coupled the sensor device to attributes outside the package housing the passageway is embedded into the package housing, wherein the top member comprising a top wall and side walls, the side walls are attached to the bottom member, and the passageway is embedded into at least one of the side walls.

A process comprises bonding a semiconductor wafer to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. After the bonding, a damage track is formed in the inorganic wafer using a laser that emits the wavelength of light. The damage track in the inorganic wafer is enlarged to form a hole through the inorganic wafer by etching. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer. An article is also provided, comprising a semiconductor wafer bonded to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. The inorganic wafer has a hole formed through the inorganic wafer. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer.

In one example, an electronic device can comprise (a) a first substrate comprising a first encapsulant extending from the first substrate bottom side to the first substrate top side, and a first substrate interconnect extending from the substrate bottom side to the substrate top side and coated by the first encapsulant, (b) a first electronic component embedded in the first substrate and comprising a first component sidewall coated by the first encapsulant, (c) a second electronic component coupled to the first substrate top side, (d) a first internal interconnect coupling the second electronic component to the first substrate interconnect, and (e) a cover structure on the first substrate and covering the second component sidewall and the first internal interconnect. Other examples and related methods are also disclosed herein.

A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.

A cavity type semiconductor package with a substrate and a cap is disclosed. The semiconductor package includes a first semiconductor die coupled to the substrate and a layer of flexible material on a surface of the cap. A trace is on the layer of flexible material. The cap is coupled to the substrate with the layer of flexible material and the trace between the cap and the substrate. A second semiconductor die is coupled to the layer of flexible material and the trace on the cap. The cap further includes an aperture to expose the second semiconductor die to the ambient environment. The layer of flexible material absorbs stress during operation cycles of the package induced by the different coefficient of thermal expansions of the cap and the substrate to reduce the likelihood of separation of the cap from the substrate.