A sensor chip includes a first substrate with a first surface and a second surface including at least one CMOS circuit, a first MEMS substrate with a first surface and a second surface on opposing sides of the first MEMS substrate, a second substrate, a second MEMS substrate, and a third substrate including at least one CMOS circuit. The first surface of the first substrate is attached to a packaging substrate and the second surface of the first substrate is attached to the first surface of the first MEMS substrate. The second surface of the first MEMS substrate is attached to the second substrate. The first substrate, the first MEMS substrate, the second substrate and the packaging substrate are provided with electrical inter-connects.

The present disclosure relates to a method for transferring a target layer to a substrate. The method includes providing a stack by forming a first transfer layer over a first substrate, forming a second transfer layer on the first transfer layer, the second transfer layer being water-soluble, and forming the target layer on the second transfer layer, such that the stack has a top surface. The method also includes bonding the top surface of the stack to a second substrate, separating the first transfer layer from the second transfer layer, and dissolving the second transfer layer in water.

The present invention discloses an SOC PMUT suitable for high-density system integration, an array chip and a manufacturing method thereof. With the SOC PMUT suitable for high-density system integration, vertical stacking and monolithic integration of a SOC PMUT array with CMOS auxiliary circuits is realized by means of direct bonding of active wafers and a vertical multi-channel metal wiring structure; in addition, the extension to the package layer is implemented by means of TSVs, without any bonding mini-pad on the periphery of the array for communication with the CMOS. Thus, the bottleneck of metal interconnections in conventional ultrasonic transducers is overcome, the chip area occupied by metal interconnections in ultrasonic transducers is greatly reduced, the metal wiring length is reduced, thus the resulting adverse effects of an electrical parasitic effect on the performance of the ultrasonic transducer array are reduced.

The present disclosure relates to a semiconductor structure for a MEMS device. In some embodiments, the structure includes an interlayer dielectric (ILD) region positioned over a substrate. Further the structure includes an inter-metal dielectric region. The IMD region includes a passivation layer overlying a stacked structure. The stacked structure includes dielectric layers and etch stop layers that are stacked in an alternating fashion. Metal wire layers are disposed within the stacked structure of the IMD region. The structure also includes a sensing electrode electrically connected to the IMD region with an electrode extension via. The structure includes a MEMS substrate comprising a MEMS device having a soft mechanical structure positioned adjacent to the sensing electrode.

A ceramic substrate is mainly constituted of ceramic, and has a first main surface and a second main surface located opposite to the first main surface. A recessed portion recessed toward a first main surface side is formed in the second main surface. A wire portion extending from an outer peripheral surface of the ceramic substrate to inside of the recessed portion is formed, and a bottom portion located on the first main surface side in the recessed portion has a portion thinner than another portion of the ceramic substrate other than the bottom portion.

A method of fabricating a semiconductor structure includes: providing a first wafer, providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer; wherein the plurality of scribe lines protrudes from a third surface of the second wafer, and the third surface is between the first surface and the second surface.

A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.

A sensor chip combining a substrate comprising at least one CMOS circuit, a MEMS substrate and another substrate comprising at least one CMOS circuit in one package that is vertically stacked is disclosed. The package comprises a sensor chip further comprising a first substrate with a first surface and a second surface comprising at least one CMOS circuit; a MEMS substrate with a first surface and a second surface; and a second substrate comprising at least one CMOS circuit. Where the first surface of the first substrate is attached to a packaging substrate and the second surface of the first substrate is attached to the first surface of the MEMS substrate. The second surface of the MEMS substrate is attached to the second substrate. The first substrate, the MEMS substrate, the second substrate and the packaging substrate are mechanically attached and provided with electrical inter-connects.

A semiconductor manufacturing method includes providing a wafer. A layer is formed over a surface of the wafer where the layer is able to form a eutectic layer with a conductive element. The layer is partially removed so as to form a plurality of mesas. The wafer is bonded to a substrate through the plurality of mesas. The substrate is thinned down to a thickness so as to be less than a predetermined value.

A component which can be produced at wafer level has a first chip and a second chip connected thereto. The connection is (at least partially) established via a first and a second connecting structure and a first and a second contact structure of the second chip. An adaptation structure between the first chip and the first connecting structure equalizes a height difference between the first and the second contact structure.