An object of the invention is to provide a coated cutting tool whose tool life can be extended by having excellent wear resistance and fracture resistance. The coated cutting tool includes: a substrate; and a coating layer formed on a surface of the substrate, in which the coating layer includes a lower layer, an intermediate layer, and an upper layer in this order from a substrate side to a surface side of the coating layer, the lower layer includes one or more Ti compound layers formed of a specific Ti compound, the intermediate layer contains TiCNO, TiCO, or TiAlCNO, the upper layer contains α-type Al.sub.2O.sub.3, an average thickness of the lower layer is 2.0 μm or more and 8.0 μm or less, an average thickness of the intermediate layer is 0.5 μm or more and 2.0 μm or less and is 10% or more and 20% or less of an average thickness of the entire coating layer, an average thickness of the upper layer is 0.8 μm or more and 6.0 μm or less, and in the intermediate layer, a ratio of a length of CSL grain boundaries and a ratio of a length of Σ3 grain boundaries are in specific ranges.

A semiconductor processing tool performs passivation layer deposition and removal in situ. A transport mechanism included in the semiconductor processing tool transfers a semiconductor structure through different deposition chambers (e.g., without breaking or removing a vacuum environment). Accordingly, the semiconductor processing tool deposits a target layer that is thinner on, or even absent from, a metal layer, such that contact resistance is reduced between a conductive structure formed over the target layer and the metal layer. As a result, electrical performance of a device including the conductive structure is improved. Moreover, because the process is performed in situ (e.g., without breaking or removing the vacuum) in the semiconductor processing tool, production time and risk of impurities in the conductive structure are reduced. As a result, throughput is increased, and chances of spoiled wafers are decreased.

A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

The invention provides process for producing a stable Si or Ge electrode structure comprising cycling a Si or Ge nanowire electrode until a structure of the Si nanowires form a continuous porous network of Si or Ge ligaments.

Electrically conductive masking tapes include an electrically conductive backing and an electrically conductive pressure sensitive adhesive layer. The pressure sensitive adhesive contains an acrylate-based copolymeric matrix, a crosslinker, an electrically conductive filler, and at least one antioxidant. The acrylate-based copolymeric matrix is the reaction product of a polymerizable mixture including at least one first alkyl(meth)acrylate monomer with a homopolymer Tg of less than −50° C., and at least one hydroxyl-functional alkyl(meth)acrylate with a homopolymer Tg of less than −10° C. The electrically conductive tape is capable of being laminated to and cleanly removed from a substrate surface, after being subjected to harsh conditions such as plasma vapor deposition conditions.

Embodiments of the present disclosure generally relate to protective coatings on substrates and methods for depositing the protective coatings. In one or more embodiments, a method of forming a protective coating on a substrate includes depositing a chromium oxide layer containing amorphous chromium oxide on a surface of the substrate during a first vapor deposition process and heating the substrate containing the chromium oxide layer comprising the amorphous chromium oxide to convert at least a portion of the amorphous chromium oxide to crystalline chromium oxide during a first annealing process. The method also includes depositing an aluminum oxide layer containing amorphous aluminum oxide on the chromium oxide layer during a second vapor deposition process and heating the substrate containing the aluminum oxide layer disposed on the chromium oxide layer to convert at least a portion of the amorphous aluminum oxide to crystalline aluminum oxide during a second annealing process.

In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

Methods of depositing a nanocrystalline diamond film are described. The method may be used in the manufacture of integrated circuits. Methods include treating a substrate with a mild plasma to form a treated substrate surface, incubating the treated substrate with a carbon-rich weak plasma to nucleate diamond particles on the treated substrate surface, followed by treating the substrate with a strong plasma to form a nanocrystalline diamond film.

A process for removal of impurities, in particular of dopants, from chlorosilanes which includes the following steps: (a) heating a deposition surface (3); (b) contacting the heated deposition surface (3) with at least one gaseous chlorosilane mixture, the gaseous chlorosilane mixture including at least one chlorosilane and at least one impurity, in particular at least one dopant; (c) at least partially removing the impurity, in particular the dopant, by forming polycrystalline silicon depositions on the deposition surface (3), the polycrystalline silicon depositions being enriched with the impurity, in particular with the dopant; (d) discharging the purified gaseous chlorosilane mixture; (e) contacting the heated deposition surface (3) with an etching gas to return the polycrystalline silicon depositions and the impurity, in particular the dopant, into the gas phase to form a gaseous etching gas mixture; and (f) discharging the gaseous etching gas mixture.

A system and method are described for depositing a material onto a receiving surface, where the material is formed by use of a plasma to modify a source material in-transit to the receiving surface. The system comprises a microwave generator electronics stage. The system further includes a microwave applicator stage including a cavity resonator structure. The cavity resonator structure includes an outer conductor, an inner conductor, and a resonator cavity interposed between the outer conductor and the inner conductor. The system also includes a multi-component flow assembly including a laminar flow nozzle providing a shield gas, a zonal flow nozzle providing a functional process gas, and a source material flow nozzle configured to deliver the source material. The source material flow nozzle and zonal flow nozzle facilitate a reaction between the source material and the functional process gas within a plasma region.