Processing methods and apparatus for depositing a protective layer on internal surfaces of a reaction chamber are provided. One method may include depositing, while no wafers are present in the reaction chamber having interior surfaces, a first layer of protective material onto the interior surfaces, the interior surfaces comprising a first material, processing, after the depositing the first layer, a portion of a batch of wafers within a reaction chamber, measuring an amount of the first material in the reaction chamber during processing the portion of the batch of wafers, or on one of the wafers in the portion of the batch of wafers, determining that the first amount exceeds a threshold, and depositing, in response to determining that the first amount exceeds the threshold and while no wafers are present in the reaction chamber, a second layer of protective material onto the interior surfaces of the reaction chamber.

Low-flow tungsten chemical vapor deposition (CVD) techniques described herein provide substantially uniform deposition of tungsten on a semiconductor substrate. In some implementations, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD). This reduces the likelihood of defect formation in the tungsten layer while increasing the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates).

Low-flow tungsten chemical vapor deposition (CVD) techniques described herein provide substantially uniform deposition of tungsten on a semiconductor substrate. In some implementations, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD). This reduces the likelihood of defect formation in the tungsten layer while increasing the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates).

Described herein is a technique capable of suppressing a deviation in a thickness of a film formed on a substrate. According to one aspect of the technique of the present disclosure, a substrate processing apparatus includes a substrate retainer capable of supporting substrates; a cylindrical process chamber including a discharge part and supply holes; partition parts arranged in the circumferential direction to partition supply chambers communicating with the process chamber through the supply holes; nozzles provided with an ejection hole; and gas supply pipes. The supply chambers includes a first nozzle chamber and a second nozzle chamber, the process gas includes a source gas and an assist gas, the nozzles includes a first nozzle for the assist gas flows and a second nozzle disposed in the second nozzle chamber and through which the source gas flows, and the first nozzle is disposed adjacent to the second nozzle.

Described herein is a technique capable of suppressing a deviation in a thickness of a film formed on a substrate. According to one aspect of the technique of the present disclosure, a substrate processing apparatus includes a substrate retainer capable of supporting substrates; a cylindrical process chamber including a discharge part and supply holes; partition parts arranged in the circumferential direction to partition supply chambers communicating with the process chamber through the supply holes; nozzles provided with an ejection hole; and gas supply pipes. The supply chambers includes a first nozzle chamber and a second nozzle chamber, the process gas includes a source gas and an assist gas, the nozzles includes a first nozzle for the assist gas flows and a second nozzle disposed in the second nozzle chamber and through which the source gas flows, and the first nozzle is disposed adjacent to the second nozzle.

A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

A vapor deposition device is provided that can suppress an influence on an epitaxial layer which is caused by a position of a lift pin without adjusting an upper and lower heating ratio of a wafer. A reaction chamber is provided with a susceptor on which a carrier is placed, and a carrier lift pin which moves the carrier vertically relative to the susceptor; and the carrier lift pin is installed outside of an outer edge of the wafer when a state where the carrier supporting the wafer is mounted on the susceptor is viewed in a plan view.

A vapor deposition device is provided that can suppress an influence on an epitaxial layer which is caused by a position of a lift pin without adjusting an upper and lower heating ratio of a wafer. A reaction chamber is provided with a susceptor on which a carrier is placed, and a carrier lift pin which moves the carrier vertically relative to the susceptor; and the carrier lift pin is installed outside of an outer edge of the wafer when a state where the carrier supporting the wafer is mounted on the susceptor is viewed in a plan view.

An impedance measurement jig may include a first contact plate, a second contact plate, a cover plate, a plug, and an analyzer. The first contact plate may make electrical contact with an ESC in a substrate-processing apparatus. The second contact plate may make electrical contact with a focus ring configured to surround the ESC. The cover plate may be configured to cover an upper surface of the substrate-processing apparatus. The plug may be installed at the cover plate to selectively make contact with the first contact plate or the second contact plate. The analyzer may individually apply a power to the first contact plate and the second contact plate through the plug to measure an impedance of the ESC and an impedance of the focus ring. Thus, the impedances of the ESC and the focus ring may be individually measured to inspect the ESC and/or the focus ring.