Fabricating a crystalline metal-phosphide layer may include providing a crystalline base substrate and a step of forming a crystalline metal-source layer. The method may further include performing a chemical conversion reaction to convert the metal-source layer to the crystalline metal phosphide layer. One or more corresponding semiconductor structures can be also provided.

A method to reduce the work function of a carbon-coated lanthanum hexaboride (LaB6) cathode wherein the exposed tip of the cathode is exposed to moisture between two heat treatments is provided. The work function may be reduced by 0.01 eV or more.

A method to reduce the work function of a carbon-coated lanthanum hexaboride (LaB6) cathode wherein the exposed tip of the cathode is exposed to moisture between two heat treatments is provided. The work function may be reduced by 0.01 eV or more.

A nano-twinned copper layer is disclosed, wherein over 50% of a volume of the nano-twinned copper layer comprises a plurality of columnar crystal grains, the plurality of columnar crystal grains connect to each other, at least 70% of the plurality of columnar crystal grains are formed by a plurality of nano-twins stacking in an orientation of a crystal axis, and an angle included between two adjacent columnar crystal grains is greater 20° and less than or equal to 60°. In addition, a method for manufacturing the nano-twinned copper layer and a substrate comprising the same are also disclosed.

A nano-twinned copper layer is disclosed, wherein over 50% of a volume of the nano-twinned copper layer comprises a plurality of columnar crystal grains, the plurality of columnar crystal grains connect to each other, at least 70% of the plurality of columnar crystal grains are formed by a plurality of nano-twins stacking in an orientation of a crystal axis, and an angle included between two adjacent columnar crystal grains is greater 20° and less than or equal to 60°. In addition, a method for manufacturing the nano-twinned copper layer and a substrate comprising the same are also disclosed.

A method for producing the growth of a semiconductor material, in particular of type II-VI, uses a melt of the semiconductor placed in a sealed bulb under vacuum or under controlled atmosphere, the bulb being subjected to a sufficient temperature gradient for first maintaining the melt in the liquid state, then causing its progressive crystallization from the surface towards the bottom. The method further comprises an element capable of floating on the surface of the melt, and equipped with a substantially central bore, intended for receiving a seed crystal for permitting the nucleation leading to the preparation of a seed crystal, and also supporting the seed crystal above the melt while maintaining it in contact with the melt in order to permit the continued crystallization from the seed crystal by lowering the temperature gradient.

The metallic crystal structures inspired edge-to-edge tessellations and a tessellation based lattice structures are disclosed. In accordance with an exemplary embodiment of the invention, basic unit lattice cells are stacked and connected to constitute a three-dimensional tessellations, wherein each of the basic unit lattice cells comprises a multiple flat connecting portions formed on a surface of the basic unit lattice cell and intersecting with a multiple of axes intersecting in a center of the basic unit lattice cell, and the flat connecting portions of one of the basic unit lattice cell is connected to the flat connecting portions of the adjacent basic unit lattice cell to constitute a connection structure of edge-to-edge tessellation. The formed tessellations are periodically tessellated in a design domain to form different tessellated lattice structures. The Functionally Tessellated (FT) lattice structures composed of different tessellations by interlocking into each other are also disclosed.

The metallic crystal structures inspired edge-to-edge tessellations and a tessellation based lattice structures are disclosed. In accordance with an exemplary embodiment of the invention, basic unit lattice cells are stacked and connected to constitute a three-dimensional tessellations, wherein each of the basic unit lattice cells comprises a multiple flat connecting portions formed on a surface of the basic unit lattice cell and intersecting with a multiple of axes intersecting in a center of the basic unit lattice cell, and the flat connecting portions of one of the basic unit lattice cell is connected to the flat connecting portions of the adjacent basic unit lattice cell to constitute a connection structure of edge-to-edge tessellation. The formed tessellations are periodically tessellated in a design domain to form different tessellated lattice structures. The Functionally Tessellated (FT) lattice structures composed of different tessellations by interlocking into each other are also disclosed.

A semiconductor interconnect and an electrode for semiconductor devices may include a thin film including a multielement compound represented by Formula 1 and having a thickness equal to or less than about 50 nm, a grain size (A) to thickness (B) ratio (A/B) equal to or greater than about 1.2, and a resistivity equal to or less than about 200 μΩ.Math.cm:
M.sub.n+1AX.sub.n  Formula 1 In Formula 1, M, A, X, and n are as described in the specification.

The present disclosure generally relates to compositions comprising substrate-free crystalline 2D bismuthene, and the method of making and using the substrate-free crystalline 2D bismuthene.