A GaN single crystal having a gallium polar surface which is a main surface on one side and a nitrogen polar surface which is a main surface on the opposite side, wherein on the gallium polar surface is found at least one square area, an outer periphery of which is constituted by four sides of 2 mm or more in length, and, when the at least one square area is divided into a plurality of sub-areas each of which is a 100 μm×100 μm square, pit-free areas account for 80% or more of the plurality of sub-areas.

A GaN single crystal having a gallium polar surface which is a main surface on one side and a nitrogen polar surface which is a main surface on the opposite side, wherein on the gallium polar surface is found at least one square area, an outer periphery of which is constituted by four sides of 2 mm or more in length, and, when the at least one square area is divided into a plurality of sub-areas each of which is a 100 μm×100 μm square, pit-free areas account for 80% or more of the plurality of sub-areas.

A nitride semiconductor template includes a heterogeneous substrate, a first nitride semiconductor layer that is formed on one surface of the heterogeneous substrate, includes a nitride semiconductor and has an in-plane thickness variation of not more than 4.0%, and a second nitride semiconductor layer that is formed on an annular region including an outer periphery of an other surface of the heterogeneous substrate, includes the nitride semiconductor and has a thickness of not less than 1 μm.

A nitride semiconductor template includes a heterogeneous substrate, a first nitride semiconductor layer that is formed on one surface of the heterogeneous substrate, includes a nitride semiconductor and has an in-plane thickness variation of not more than 4.0%, and a second nitride semiconductor layer that is formed on an annular region including an outer periphery of an other surface of the heterogeneous substrate, includes the nitride semiconductor and has a thickness of not less than 1 μm.

It is an object to provide a ferroelectric thin film having much higher ferroelectric properties than conventional Sc-doped ferroelectric thin film constituted by aluminum nitride and also having stability when applied to practical use, and also to provide an electronic device using the same.

There are provided a ferroelectric thin film represented by a chemical formula M1.sub.1-XM2.sub.XN, wherein M1 is at least one element selected from Al and Ga, M2 is at least one element selected from Mg, Sc, Yb, and Nb, and X is within a range of 0 or more and 1 or less, and also an electronic device using the same.

In a general aspect, a ceramic thin film with nanotwinned regions at a tunable volume fraction is manufactured. In some aspects, a method for manufacturing a ceramic thin film on a surface of a substrate in an evacuated chamber is disclosed. The ceramic thin film includes crystalline grains; and each of the crystalline grains includes one or more nanotwinned regions. The one or more nanotwinned regions have a volume fraction in a range of 30-80% of the ceramic thin film. The ceramic thin film comprises titanium, nitrogen, and boron. A plurality of targets including a plurality of sputtering materials is prepared. A gas atmosphere in the evacuated chamber is formed. Electric power is supplied to the plurality of targets to cause co-sputtering of the plurality of sputtering materials to form the ceramic thin film with the one or more nanotwinned regions.

In a general aspect, a ceramic thin film with nanotwinned regions at a tunable volume fraction is manufactured. In some aspects, a method for manufacturing a ceramic thin film on a surface of a substrate in an evacuated chamber is disclosed. The ceramic thin film includes crystalline grains; and each of the crystalline grains includes one or more nanotwinned regions. The one or more nanotwinned regions have a volume fraction in a range of 30-80% of the ceramic thin film. The ceramic thin film comprises titanium, nitrogen, and boron. A plurality of targets including a plurality of sputtering materials is prepared. A gas atmosphere in the evacuated chamber is formed. Electric power is supplied to the plurality of targets to cause co-sputtering of the plurality of sputtering materials to form the ceramic thin film with the one or more nanotwinned regions.

It is provided a seed crystal layer, composed of a group 13 nitride crystal selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof, on an alumina layer on a single crystal substrate. By annealing under reducing atmosphere at a temperature of 950° C. or higher and 1200° C. or lower, convex-concave morphology is formed on a surface of the seed crystal layer so as to have an RMS value of 180 nm to 700 nm measured by an atomic force microscope. On the surface of the seed crystal layer, it is grown a group 13 nitride crystal layer composed of a group 13 nitride crystal selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof.

It is provided a seed crystal layer, composed of a group 13 nitride crystal selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof, on an alumina layer on a single crystal substrate. By annealing under reducing atmosphere at a temperature of 950° C. or higher and 1200° C. or lower, convex-concave morphology is formed on a surface of the seed crystal layer so as to have an RMS value of 180 nm to 700 nm measured by an atomic force microscope. On the surface of the seed crystal layer, it is grown a group 13 nitride crystal layer composed of a group 13 nitride crystal selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof.

A vapor phase epitaxial growth device comprises a reactor vessel and a wafer holder arranged within the reactor vessel. The wafer holder includes a wafer holding surface configured to hold a wafer with a wafer surface oriented substantially vertically downward. The device comprises a first material gas supply pipe configured to supply a first material gas and arranged below the wafer holding surface. The device comprises a second material gas supply pipe configured to supply a second material gas and arranged below the wafer holding surface. The device comprises a gas exhaust pipe configured to exhaust gases and arranged below the wafer holding surface. A distance between the gas exhaust pipe and an axis line passing through a center of the wafer holding surface is greater than distances between the axis line and each of the first material gas supply pipe and the second material gas supply pipe.