In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (R.sub.DEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (R.sub.PTAT) of the differential amplifier stage, a third resistor (R1.sub.PTAT) of the scaling amplifier stage, and a fourth resistor (R2.sub.PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.

An arc fault detection system senses current flow in a power source branch and in one or more load branches in an electrical system. Over a frequency range divided into a predetermined number of frequency bins, a controller records and tallies the branch having largest magnitude of power spectral density for each frequency bin. The branch having highest total tally is determined to be the branch in which the arc fault occurred and can then safely be isolated from the electrical system.

A current detection circuit includes a current sampling branch, a switch branch, a first current mirror branch, a capacitor branch, a feedback branch and a control branch. The control branch receives the second current and outputs the first current and the first voltage signal. The current sampling branch outputs a first discharging current. The switch branch establishes and disconnects the connection between the first current mirror branch and the capacitor branch. The capacitor branch is charged in response to the first charging current and discharged in response to the first discharging current. The first current mirror branch outputs the first charging current. The feedback branch adjusts the second charging current to adjust the first charging current, so that the total charge of the capacitor branch is balanced with the total charge of discharge within one switching cycle, so that the first current is represented by the first charging current.

A switched-capacitor converter has a first and second terminal; a switched-capacitor ladder network having a plurality of serially connected first capacitors defining a plurality of flying capacitor nodes; a plurality of serially connected second capacitors defining a plurality of output capacitor nodes, wherein nodes of the flying capacitor nodes can be connected to nodes of the output capacitor nodes in a plurality of ladder converter configurations to perform a switched-capacitor ladder power conversion; and a switch matrix to connect the first terminal to different flying capacitor nodes and/or to connect any flying capacitor node to any other flying capacitor node or output capacitor node according to different switch configurations. Also, a switched-capacitor converter assembly may have a plurality of serially and/or parallel connected switched-capacitor reconfigurable switched-capacitor ladder converters. Methods for converting an input into an output voltage using a converter and for operating an assembly of converters are also provided.

Circuits and methods for reducing lagging responses of a power converter to changes in circuit voltages or current, over-shoot/under-shoot when a target output voltage changes faster than the power converter's response, and open loop conditions. Embodiments include scanning a feedback voltage from a load powered by a voltage output by a power converter controlled by a PWM control signal; detecting an under-regulation condition; and, while the under-regulation condition is detected, increasing a clock signal rate to a counter outputting a count value usable to generate the PWM control signal. Embodiments include comparing a target output voltage to a signal representative of an output voltage of the power converter; indicating an under-shoot or over-shoot condition if the voltage difference exceeds a corresponding offset value; and limiting the range of values for an M-bit count value used to generate the PWM control signal to mitigate the under-shoot or over-shoot condition.

A synchronous rectifier includes: an integrator configured to integrate a voltage across a secondary side winding of a transformer over an integral period having an expected zero integral value; a first comparator configured to detect an end of a demagnetization phase of the secondary side winding based on diode detection; and a digital circuit configured to adjust a channel gain of the synchronous rectifier based on an integration error at the end of the integral period, the integration error corresponding to the difference between the integrated voltage at the end of the integral period and the expected zero integral. Corresponding methods of gain tuning and a power converter are also described.

The invention relates to a system 1 for controlling a voltage converter comprising a plurality of high-side switches forming a high group and a plurality of low-side switches forming a low group, the control system 1 comprising: a module 10 for measuring a voltage V of the DC voltage source B, a module 11 for comparing the measured voltage V with a first safety threshold OV1, a control module 12 for controlling a first group of switches so as to close chosen from the high group or the low group, if the comparison module 11 indicates that the measured voltage V is higher than the first safety threshold OV1.

A system includes a memory device and a processing device, operatively coupled to the memory device, the processing device to perform operations comprising: measuring one of a temperature voltage shift or a read bit error rate of fixed data stored in the memory device in response to detecting a power on of the memory device, the fixed data having been programmed in response to detecting a power loss; estimating an amount of time for which the memory device was powered off based on results of the measuring; and in response to the amount of time satisfying a threshold criterion, updating a value for a temporal voltage shift of a block family based on the amount of time.

A wide input voltage range power converter circuit in a one-stage-two-switch configuration has a power input terminal, a switch node connected to the power input terminal, a transformer, two electronic switches, a pulse width modulation (PWM) circuit, and an output circuit. An input side of the transformer has a first winding and a second winding that are connected to the switch node. An output side of the transformer has an output winding. A turns ratio between the first winding and the output winding is different from a turns ratio between the second winding and the output winding. The two electronic switches are respectively connected to the first winding and the second winding in series. The PWM circuit is connected to the power input terminal and control terminals of the two electronic switches. The output circuit is connected to the output winding.

A memory system includes a connector through which power for the memory system is to be supplied from an external device, a controller, a nonvolatile memory device, a power source circuit connected to the controller and the nonvolatile memory device by power lines through which power is supplied to the controller and the nonvolatile memory device, and a power source control circuit that receives a supply of power from the external device through the connector and supplies the power to the power control circuit. The power source control circuit is configured to detect using a divided voltage of a voltage of the power supplied thereto, that the voltage of the power supplied thereto is higher than a predetermined voltage and interrupt the power supplied to the power control circuit if the voltage of the power supplied thereto is higher than the predetermined voltage.