Detection circuitry for an integrated circuit (IC) includes voltage divider circuitry, comparison circuitry, and calibration circuitry. The voltage divider circuitry receives a power supply signal and output a first reference voltage signal and a supply voltage signal based on the power supply signal. The comparison circuitry compares the first reference voltage signal and the supply voltage signal to generate an output signal. The calibration circuitry alters one or more parameters of the voltage divider circuitry to increase a voltage value of the supply voltage signal based on the comparison of the first reference voltage signal with the supply voltage signal.

Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

A semiconductor integrated circuit device includes a control unit configured to control a switching element or an output transistor of a power supply device, a monitor terminal for monitoring an output voltage of the power supply device, a test unit configured to output a test signal to the monitor terminal before activation of the power supply device, and a determination unit configured to determine whether or not the monitor terminal is open, on the basis of a voltage of the monitor terminal when the test unit outputs the test signal to the monitor terminal.

A system includes a memory device and a processing device, operatively coupled to the memory device, the processing device to perform operations comprising: measuring one of a temperature voltage shift or a read bit error rate of fixed data stored in the memory device in response to detecting a power on of the memory device, the fixed data having been programmed in response to detecting a power loss; estimating an amount of time for which the memory device was powered off based on results of the measuring; and in response to the amount of time satisfying a threshold criterion, updating a value for a temporal voltage shift of a block family based on the amount of time.

The present invention provides a glitch detector including a first inverter, a second inverter, a first capacitor and a second capacitor. The first inverter is connected between a supply voltage and a ground voltage, and is configured to receive a first signal at a first node to generate a second signal to a second node. The second inverter is connected between the supply voltage and the ground voltage, and is configured to receive the second signal at the second node to generate the first signal to the first node. A first electrode of the first capacitor is coupled to the supply voltage, and a second electrode of the first capacitor is coupled to the first node. A first electrode of the second capacitor is coupled to the ground voltage, and a second electrode of the second capacitor is coupled to the second node.

Disclosed is a power failure detection circuit, including a first PMOS FET (mp1), a second PMOS FET (mp2), a first NMOS FET (mn2), a second NMOS FET (mn3) and a reset transistor (mn1). The PN junction area of the drain electrode of the first PMOS FET (mp1) is greater than the PN junction area of the drain electrode of the first NMOS FET (mn2). The PN junction area of the drain electrode of the second NMOS FET (mn3) is greater than the PN junction area of the drain electrode of the second PMOS FET (mp2). The power failure detection circuit of the present invention is novel in design and high in practicability.

A measuring device facilitates equipment calibration. A measuring device for measuring noise contained in equipment having a prescribed resistance value is provided with a first voltage-dividing circuit connected to a direct-current power source, a second voltage-dividing circuit connected in parallel with the first voltage-dividing circuit , and a measuring unit which measures a first voltage-divided voltage output from the first voltage-dividing circuit, and a second voltage-divided voltage output from the second voltage-dividing circuit, a calculating unit which calculates the difference between the measured first voltage-divided voltage and second voltage-divided voltage, and an output unit which outputs the calculated result, wherein: the first voltage-dividing circuit outputs the first voltage-divided voltage from the equipment and a first resistor, connected in series.

A chip with power-glitch detection is provided, which includes a power terminal receiving power, an inverter, and a back-up power storage device coupled to the power terminal. The inverter has an input terminal coupled to the power terminal. The back-up power storage device transforms the power to back-up power. The inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the inverter.

A system is described. The system includes a control transistor, a voltage source, a feedback node connected between a drain of the control transistor and the voltage source, a plurality of resistors connected between the voltage source and ground, and a control node connected to a gate of the control transistor. The resistors include a first series-connected set of resistors associated with the control transistor being biased and a second series-connected set of resistors associated with the control transistor being unbiased. During a startup period, the control node is configured to bias the control transistor to select the first series-connected set of resistors, thereby increasing a voltage level of the voltage source to a boosted VCC voltage. After the startup period, the control node is configured to unbias the control transistor to select the second series-connected set of resistors, thereby decreasing the boosted VCC voltage to a normal VCC voltage.

A voltage level detector includes a voltage divider that generates a first division voltage and a second division voltage. A first comparator compares any one of the first and second division voltages with a reference. A second comparator compares the other of the first and second division voltages with the reference. A first switch converts a connection path between the first and second division voltages and the first and second comparators based on a clock signal. A determination circuit determines, based on a first comparison signal and a second comparison signal, whether the voltage level detector is normal. A second switch converts a connection path between the first and second comparison signals and input terminals of the determination circuit based on the clock signal.