A test and measurement system has one or more inputs connectable to a device under test (DUT), and one or more processors configured to execute code that causes the one or more processors to: gather a set of training waveforms by acquiring one or more waveforms from one or more DUTs or from simulated waveforms, remove noise from the set of training waveforms to produce a set of noiseless training waveforms, and use the set of noiseless training waveforms as a training set to train a neural network to predict a measurement value for a DUT, producing a trained neural network. A method of training a neural network having receiving one or more waveforms from one or more DUTs, or generating one or more waveforms from a waveform simulator, removing noise from a set of training waveforms gathered from the one or more waveforms to produce a set of noiseless training waveforms, and use the set of noiseless training waveforms as a training set to train a neural network to predict a measurement value for a DUT, producing a trained neural network.

A test and measurement circuit including a capacitor in parallel with a device under test, a direct current voltage source configured to charge the capacitor, a pulse generator configured to generate a pulse for testing the device under test, and a sensor for determining a current in the device under test.

A method analyzes an operation of a power semiconductor device. The method includes: providing a set of reference voltages of the device and a set of corresponding reference currents; measuring, within a predetermined time-interval, Nframe on-state voltages and Nframe corresponding on-state currents of the device to obtain Nframe measurement points, Nframe being an integer number equal to or greater than 2; adapting the set of reference voltages by carrying out a least squares fit to the Nframe measurement points; and using the adapted set of reference voltages to analyze the operation of the power semiconductor device.

A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.

A testing method and testing system for a semiconductor element are provided. The method includes following steps. A level of a testing electrostatic discharge (ESD) voltage is determined. A plurality of sample components is provided. The testing ESD voltage is imposed on the sample components for testing ESD decay rates of the sample components. ESD withstand voltages of the sample components are detected. The relation between the ESD withstand voltages and the electrostatic discharge rates are recorded to a database. The testing ESD voltage is imposed on the semiconductor element for testing an ESD decay rate of the semiconductor element. The database is looked up according to the ESD decay rate of the semiconductor element to determine an ESD withstand voltage of the semiconductor element.

The present disclosure provides a switching matrix system and an operating method thereof for semiconductor characteristic measurement. The switching matrix system is configured to: detect an assembly of at least one switching matrix module inserted into a plurality of slots of the switching matrix system; determine a user interface according to the assembly of the at least one switching matrix module inserted into the slots, wherein the user interface includes an operable object corresponding to the assembly; and provide the user interface.

A method for diagnosing an open-circuit fault of a switching transistor of a single-phase half-bridge five-level inverter is provided. It includes the following steps. A semi-physical experiment platform with a DSP controller and an RT-LAB real-time simulator as its core constructed, and an output side voltage is selected as a fault signal variable. Empirical mode decomposition is used to extract a fault feature vector, and then a HHT time-frequency diagram of the fault feature vector is extracted, a voltage signal is converted into spectrum data, and time-frequency diagram fuzzy sets corresponding to different fault types are obtained. Fusion of the time-frequency diagram fuzzy sets of the same fault type is performed to obtain a fusion image that contains more fault features. The fusion images corresponding to all fault types are inputted into the deep convolutional neural network for training and testing, and a fault diagnosis result is obtained.

A method for determining a corrected current-voltage curve of an electrical system, the method including the following steps: obtaining a first current-voltage characteristic curve of the electrical system, by varying the voltage across its terminals at a first measurement rate, obtaining a second current-voltage characteristic curve of the electrical system, by varying the voltage across its terminals at a second measurement rate, different from the first rate, using a single notional capacitance to model an intrinsic stray effect to be corrected between an input voltage without the stray effect and the output voltage, determining a correction value representative of the stray effect and a step of determining a corrected current value on the basis of the determined correction value.

The disclosed technology relates to a method and apparatus for graphically displaying a switching cycle of a switching device. A switching voltage and a switching current are acquired for a device under test via a voltage probe and a current probe, respectively, for a plurality of switching cycles of the device under test. The switching current versus the switching voltage is plotted on a current versus voltage plot as a curve for each of the switching cycles. Each of the curves on the current versus voltage plot overlap each other and are displayed to a user.

A signal analyzer for analyzing an input signal comprises at least one input for receiving the input signal, at least one acquisition unit for acquiring data assigned to the input signal, an acquisition memory for storing the acquired data, the acquisition memory being adapted to store data in at least one ring buffer, and an acquisition memory controller to control at least one of writing the acquired data in the acquisition memory and reading the acquired data from the acquisition memory. The acquisition memory controller comprises a data read module for reading data of the at least one ring buffer. The acquisition memory controller comprises a copy write module which taps data read by the data read module. The acquisition memory comprises an additional memory section. The copy write module is configured to write the data tapped into the additional memory section. Further, a method of processing data from an input signal is described.