Probe cards for probing highly-scaled integrated circuits are provided. A probe card includes a backplane and an array of probes extending from the backplane. Each of the probes includes a cantilever member and a probe tip. A first end of the cantilever member is coupled to the backplane, such that the cantilever member extends from the backplane. The probe tip extends from a second end of the cantilever member. The probes are fabricated from semiconductor materials. Each probe is configured to transmit electrical signals between the backplane and a device under test (DUT), via corresponding electrodes of the DUT. The probes are highly-scaled such that the feature size and pitch of the probes matches the highly-scaled feature size and pitch of the DUT's electrodes. The probes comprise atomic force microscopy (AFM) probes that are enhanced for increased electrical conductivity, elasticity, lifetime, and reliability.

Enhanced probe cards, for testing unpackaged semiconductor die including numerous discrete devices (e.g., LEDs), are described. The die includes anodes and cathodes for the LEDs. Via a single touchdown event, the probe card may simultaneously operate each of the LEDs. The LEDs' optical output is measured and the performance of the die is characterized. The probe card includes a conductive first contact and another contact that are fabricated from a conformal sheet or film. Upon the touchdown event, the first contact makes contact with each of the die's anodes and the other contact makes contact with each of the die's cathodes. The vertical and sheet resistance of the contacts are sufficient such that the voltage drop across the vertical dimension of the contacts is approximately an order of magnitude greater than the operating voltage of the LEDs and current-sharing between adjacent LEDs is limited by the sheet resistance.

Enhanced probe cards, for testing unpackaged semiconductor die including numerous discrete devices (e.g., LEDs), are described. The die includes anodes and cathodes for the LEDs. Via a single touchdown event, the probe card may simultaneously operate each of the LEDs. The LEDs' optical output is measured and the performance of the die is characterized. The probe card includes a conductive first contact and another contact that are fabricated from a conformal sheet or film. Upon the touchdown event, the first contact makes contact with each of the die's anodes and the other contact makes contact with each of the die's cathodes. The vertical and sheet resistance of the contacts are sufficient such that the voltage drop across the vertical dimension of the contacts is approximately an order of magnitude greater than the operating voltage of the LEDs and current-sharing between adjacent LEDs is limited by the sheet resistance.

A test board configured to test a device under test includes: a connection region including first and second connection terminals for contacting the device under test; and a first surface mount device located adjacent to the connection region, wherein the first connection terminal is configured to be electrically connected to a first voltage regulator of the device under test, wherein the second connection terminal is configured to be electrically connected to a second voltage regulator of the device under test, and wherein the first surface mount device is configured to be electrically connected to each of the first and second connection terminals.

A test board configured to test a device under test includes: a connection region including first and second connection terminals for contacting the device under test; and a first surface mount device located adjacent to the connection region, wherein the first connection terminal is configured to be electrically connected to a first voltage regulator of the device under test, wherein the second connection terminal is configured to be electrically connected to a second voltage regulator of the device under test, and wherein the first surface mount device is configured to be electrically connected to each of the first and second connection terminals.

A computer-implemented method for assessing at least one printed circuit board includes receiving input data based on testing data of a printed circuit board, wherein the testing data represent in-circuit test testing data and include measurement data of a plurality of electronic components of the printed circuit board, applying a trained classification function to the input data, and generating and providing output data. The output data include an assignment of at least one of the electronic components to one of at least two different classes.

A power stage includes a control device and a power transistor, the control device comprising a primary circuit comprising: a control module able to generate a control current, a primary circuit malfunction detector able to detect a malfunction, a pulse transformer comprising a primary winding connected to the primary circuit, comprising a secondary winding connected to the secondary circuit, magnetically coupled to the primary winding and able to generate, from the control current, an induced pulse current making it possible to drive the power transistor, a secondary circuit comprising: a power and fault detection controller able to detect a malfunction of the secondary circuit or of the power transistor, the power and fault detection controller being able to communicate the malfunction of the secondary circuit or of the power transistor to the primary circuit malfunction detector.

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

Disclosed is a detector 10 using a liquid spray 2000 for detecting electrical faults or shorts with the detector including a body 100 having an interior 120; a hose or pipe 130 fluidly connected to interior 120; a trigger valve 140 operatively connected to hose 130; a conductor 200 attached to detector 10; and/or a pump 110 fluidly connected to interior 120. In various embodiments the detector 10 can cause liquid spray 2000 to be sprayed on a subregion of an item such as a remotely operated vehicle to create a closed electrical circuit through the liquid spray and the conductor in the detector.

A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.