An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.

To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

A power conversion device including a switching element includes: a temperature change estimation unit estimating temperature change in a semiconductor chip containing the switching element; a number calculator calculating the number of power cycles to fracture of the semiconductor chip due to power cycles; and a degradation degree calculator computing a degree of degradation of the semiconductor chip caused by the power cycles. The temperature change estimation unit calculates a maximum value and a minimum value of temperature of the semiconductor chip in one power cycle based on a first threshold of temperature fall allowed when it is determined that the temperature of the semiconductor chip is rising, and a second threshold of temperature rise allowed when it is determined that the temperature of the semiconductor chip is falling. The number calculator calculates the number of power cycles to fracture based on the maximum value and the minimum value.

A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

The present disclosure discloses a test socket including an inelastic insulating housing formed of an inelastic insulating material having a plurality of housing holes, and a plurality of electro-conductive parts comprising electro-conductive particles in an elastic insulating material, the electro-conductive parts including an electro-conductive part body having a lower end portion to be connected to a signal electrode of the tester, an upper end portion to be connected to the terminal of the device under inspection, and an electro-conductive part bump connected to the electro-conductive part body to protrude from one or both of an upper and lower surface of the inelastic insulating housing.

The present disclosure relates to an optical sensor, comprising: a first circuit board having at least a data processing unit and an interface to a second circuit board, wherein the interface is connected with the data processing unit; and the second circuit board having an LED, a thermistor and a capacitor, which is connected in parallel with the thermistor, wherein the capacitor is embodied specifically for the LED, and an interface to the first circuit board, wherein LED, thermistor and capacitor are connected with the interface. The present disclosure relates also to a method for identifying an LED in an optical sensor.

The present disclosure discloses a test apparatus for testing a package-on-package (POP) type semiconductor package includes a lower socket mounted to a tester board providing a test signal, and provided with a plurality of socket pins connected to a lower terminal of a lower package to electrically connect the lower package and the tester board to each other; a pusher to which an upper package is coupled, the pusher having a pusher body which may be moved to approach the lower socket or to be moved away from the lower socket; and an upper socket coupled to the pusher body, and provided with an insulating pad formed of a nonelastic insulating material and a plurality of electrically-conductive parts supported on the insulating pad, the electrically-conductive part being formed of an elastic insulating material containing a plurality of electrically-conductive particles.

The present disclosure discloses a test apparatus for testing a package-on-package (POP) type semiconductor package includes a lower socket mounted to a tester board providing a test signal, and provided with a plurality of socket pins connected to a lower terminal of a lower package to electrically connect the lower package and the tester board to each other; a pusher to which an upper package is coupled, the pusher having a pusher body which may be moved to approach the lower socket or to be moved away from the lower socket; and an upper socket coupled to the pusher body, and provided with an insulating pad formed of a nonelastic insulating material and a plurality of electrically-conductive parts supported on the insulating pad, the electrically-conductive part being formed of an elastic insulating material containing a plurality of electrically-conductive particles.

Described herein are a system and method of preparing integrated circuits (ICs) so that the ICs remain electrically active and can have their active circuitry probed for diagnostic and characterization purposes using charged particle beams. The system employs an infrared camera capable of looking through the silicon substrate of the ICs to image electrical circuits therein, a focused ion beam system that can both image the IC and selectively remove substrate material from the IC, a scanning electron microscope that can both image structures on the IC and measure voltage contrast signals from active circuits on the IC, and a means of extracting heat generated by the active IC. The method uses the system to identify the region of the IC to be probed, and to selectively remove all substrate material over the region to be probed using ion bombardment, and further identifies endpoint detection means of milling to the required depth so as to observe electrical states and waveforms on the active IC.