A test method for a semiconductor device includes determining a contact failure between a first semiconductor chip and a second semiconductor chip during assembly of a semiconductor package including the first semiconductor chip and the second semiconductor chip, using a test circuit embedded in the first semiconductor chip, and after the assembly of the semiconductor package, determining whether the semiconductor package is defective by using the test circuit.

In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.

A display device and a testing method for a display panel are provided. The testing method for the display panel includes the steps of: storing an image signal for controlling the display panel to display a default image in a driver chip of the display panel, providing a power signal and a clock signal to the display panel, and retrieving the image signal and testing the display panel according to a preset test condition.

Machine with flying probes for testing electronic boards comprising a conveyor for loading/unloading the boards into/from the testing station, a plurality of flying probes suitable to interact with predetermined points of each board and a plurality of contacting devices arranged at the sides of the working volume of the flying probes and suitable to cooperate with contact areas arranged on one edge of the board.

An inspection data output device according to an embodiment includes an input unit, a generation unit, and an output unit. Information on a portion to be inspected in a circuit board is supplied to the input unit. The generation unit generates emphasis data in which an output signal path being a signal path on the circuit board and being a signal path capable of detecting an output signal of the portion to be inspected is emphasized more than another signal path. The output unit outputs the emphasis data to a display device.

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

Provided is a method and device for determining the cause of a fault in an electrical circuit by a graph-based circuit diagram simulation model of the electrical circuit. A fault is simulated in the electrical circuit and resulting connected components, and respective potential values and/or phase values of the graph vertices of the resulting connected components, are determined by reference to the modified graph-based circuit diagram simulation model, and, on the basis of the potential values and/or phase values of the graph vertices determined, the switching behavior of the electrical circuit is represented by the further addition and/or removal of at least one further graph edge. The resulting potential and/or phase values for specified graph vertices are outputted in the form of simulated output signals. The simulated output signals are compared with reference output signals for the electrical circuit, and the cause of the fault is outputted.

A test method for a semiconductor device includes determining a contact failure between a first semiconductor chip and a second semiconductor chip during assembly of a semiconductor package including the first semiconductor chip and the second semiconductor chip, using a test circuit embedded in the first semiconductor chip, and after the assembly of the semiconductor package, determining whether the semiconductor package is defective by using the test circuit.

A test method for a semiconductor device includes determining a contact failure between a first semiconductor chip and a second semiconductor chip during assembly of a semiconductor package including the first semiconductor chip and the second semiconductor chip, using a test circuit embedded in the first semiconductor chip, and after the assembly of the semiconductor package, determining whether the semiconductor package is defective by using the test circuit.

A compensation device (20) for compensating for leakage currents has a differential current measuring device (22), a supply network detection device (42; 45), a control device (26), an amplifier (27), a compensation current selection device (36) and a feed-in device (39, 41). The supply network detection device (42; 45) generates a second signal (V_GRID; V_ES) characterizing the supply network (L1, L2, L3, N) connected to the active conductors (51, 52, 53, 54) and to supply it to the control device (26). The compensation current selection device (36) feeds in the compensation current (I_COMP) on the basis of a third signal (V_SEL) on at least one of the at least two different active conductors (51, 54), and the third signal (V_SEL) is dependent on the second signal (V_GRID; V_ES) to select at least one active conductor (51, 54) suitable for the connected supply network for the feed-in operation.