An exemplary method of detecting a Trojan circuit in an integrated circuit is related to applying a test pattern comprising an initial test pattern followed by a corresponding succeeding test pattern to a golden design of the integrated circuit, wherein a change in the test pattern increases side-channel sensitivity; measuring a side-channel parameter in the golden design of the integrated circuit after application of the test pattern; applying the test pattern to a design of the integrated circuit under test; measuring the side-channel parameter in the design of the integrated circuit under test after application of the test pattern; and determining a Trojan circuit to be present in the integrated circuit under test when the measured side-channel parameters vary by a threshold.

A computer-implemented method for assessing at least one printed circuit board includes receiving input data based on testing data of a printed circuit board, wherein the testing data represent in-circuit test testing data and include measurement data of a plurality of electronic components of the printed circuit board, applying a trained classification function to the input data, and generating and providing output data. The output data include an assignment of at least one of the electronic components to one of at least two different classes.

A method of debugging a printed circuit board with at least one boundary-scan compliant device is presented. The method uses an electronic processing unit and includes the steps of: retrieving boundary-scan properties of the at least one boundary-scan compliant device, the properties including a listing of boundary-scan compliant circuit terminals of the at least one boundary-scan compliant device; retrieving connectivity properties; selecting and displaying a circuit graph of at least a part of the devices mounted on the printed circuit board, the circuit graph including at least one of the devices mounted on the printed circuit board and a least one further device from the devices which has a circuit terminal interconnected to a circuit terminal of the device for visualizing at least the device, the further device and interconnects between the circuit terminals of the devices.

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

In accordance with at least one aspect of this disclosure, a failure detection system for an integrated circuit component includes an integrated circuit component configured to connect to a circuit board, a first sensor operatively connected to sense and output a signal indicative of an actual current output of the component in a first state, and a second sensor operatively connected to sense and output a signal indicative of an actual condition of the component in the first state. A logic module can be configured to output a component failed state signal based at least in part on the signal indicative of the actual current output of the component in the first state and the signal indicative of the actual condition of the component in the first state.

An apparatus includes a test head frame and a tray slidably coupled to the frame and configured to receive a printed circuit board (PCB) to be tested. The PCB is positioned within the frame when the tray is in a retracted position and outside the frame when the tray is in an ejected position. A bed of nails (BON) opposes a lower side of the PCB and includes a plurality of pins having first portions arranged on an upper side of the BON to connect with corresponding electrical pads on the lower side of the PCB when the tray containing the PCB is in the retracted position. A plurality of interface printed circuit boards is configured for connection to second portions of the plurality of pins exposed on a lower side of the BON and for receiving test signals when the tray containing the PCB is in the retracted position.

A test coupon includes a pseudo element circuit which is constituted of a main circuit section and an adjusting section. The main circuit section includes a first pattern conductor and second pattern conductors. The first pattern conductor and the second pattern conductors overlap one another with a dielectric layer interposed therebetween. The first pattern conductor electrically conducts to the second pattern conductors. The main circuit section represents the R-component and the L-component of an equivalent circuit, and is a dominant circuit element which determines a signal waveform. The adjusting section includes linear conductors. A peak of a voltage waveform is suppressed by the R- and L-components of the adjusting section.

A fault rules engine generates a plurality of fault rules files. Each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design, and each fault rules file of the plurality of fault rules files can include data quantifying a nominal delay for a given two-cycle test pattern of a set of two-cycle test patterns and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects for a given cell type in the IC design. An IC test engine generates cell-aware test patterns based on the plurality of fault rules files to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of the plurality of candidate defects characterized in the plurality of fault rules files.

A compensation device (20) for compensating for leakage currents has a differential current measuring device (22), a supply network detection device (42; 45), a control device (26), an amplifier (27), a compensation current selection device (36) and a feed-in device (39, 41). The supply network detection device (42; 45) generates a second signal (V_GRID; V_ES) characterizing the supply network (L1, L2, L3, N) connected to the active conductors (51, 52, 53, 54) and to supply it to the control device (26). The compensation current selection device (36) feeds in the compensation current (I_COMP) on the basis of a third signal (V_SEL) on at least one of the at least two different active conductors (51, 54), and the third signal (V_SEL) is dependent on the second signal (V_GRID; V_ES) to select at least one active conductor (51, 54) suitable for the connected supply network for the feed-in operation.

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.