Cochlear implant systems can include a cochlear electrode and a stimulator in electrical communication with the cochlear electrode. The stimulator can be in communication with a controller, which is in communication with a testing circuit and a switching network. The stimulator can include a plurality of source elements. The controller can control the switching network to place the plurality of source elements into communication with the testing circuit. The controller can further cause one of the plurality of source elements to emit an electrical current and can determine an amount of electrical current emitted from the source element using the testing circuit. The controller can compare the determined amount of electrical current emitted by the source element with a prescribed current. The controller can adjust the output of each of the plurality of source elements based on the determined amount of electrical current emitted by the stimulator.

A detection circuit is provided in the invention. The detection circuit includes a synchronous circuit, a comparison circuit and a fail-signal generating circuit. The comparison circuit is coupled to the synchronous circuit. The comparison circuit compares a target signal with a reference signal to generate a comparison result. The frequency of the reference signal is lower than the frequency of the target signal. The fail-signal generates circuit is coupled to the synchronous circuit and the comparison circuit. The fail-signal receives the comparison circuit. According to the comparison circuit, the fail-signal determines whether the target signal has failed.

Methods and systems for electronic engine control (EEC) systems are disclosed. An EEC monitors and controls operation of an end effector, such as a torque motor. The EEC is configured to command a switchover from an active channel to a standby channel, or vice versa, in response to a trigger (e.g., a command or a fault). The switchover is executed automatically upon identification of the trigger due to the detection of a fault without the need of a command, over a predetermined time or number of cycles within a command signal.

Disclosed is a capability test method based on a joint test support platform. The method includes steps of describing an initial capability in a test, combining a capability to be developed based on the initial capability, and determining an evaluation strategy and a joint task background information of the test. Further, the method includes generating a logical shooting range for the joint test support platform according to the joint task background information, developing a test scenario according to the joint task background information and the logical shooting range, decomposing the test scenario, determining a test plan corresponding to the test scenario, executing the test according to the test plan, analyzing and evaluating a test result of the test, and generating one or more joint capability evaluation reports for the test.

A circuit chip is connected to a sensor chip in a sub-unit via a communication terminal, and includes an output wave formation circuit that performs communication by controlling a voltage of a power supply supplied from an electronic control unit (ECU) to raise a voltage level of an output signal. When the voltage of the power supply monitored by a voltage monitor rises above a threshold value, a control circuit lowers a voltage of a signal from the output wave formation circuit, thereby preventing an excessive rise of the power supply voltage used in a signal communication.

An electronic apparatus is provided. The electronic apparatus includes a communication interface configured to communicate with an external device, a memory, and a processor. The processor is configured to transmit a control signal requesting the external device to apply a first signal to a transparent electrode sheet connected to the external device, to the external device, receive, from the external device, a first point at which the first signal is applied to the transparent electrode sheet, a second point at which a second signal that is a response signal to the first signal is acquired by the external device, and a waveform of the second signal, and identify whether a defect exists in the transparent electrode sheet based on a difference between the first point and the second point, and the waveform of the second signal.

The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

An apparatus performs methods for device diagnostics based on signals from digital outputs. The apparatus includes an input/output module with a digital output module to be coupled to a device. The input/output module measures one or more characteristics of a digital signal provided by the digital output module, where at least one of the one or more characteristics of the digital signal is associated with an output current of the digital output module. The input/output module also performs one or more diagnostics using the one or more measured characteristics of the digital signal.

De-embedding apparatus and methods of de-embedding are disclosed. A de-embedding apparatus includes a test structure including a device-under-test (DUT) embedded in the test structure, and a plurality of dummy test structures including an open dummy structure, a distributed open dummy structure, and a short dummy structure. The distributed open dummy structure may include a first signal transmission line coupled to a left signal test pad and a second signal transmission line coupled to a right signal test pad, the first and second signal transmission lines having a smaller total length than a total length of signal transmission lines of the open dummy structure, and intrinsic transmission characteristics of the DUT can be derived from transmission parameters of the dummy test structures and the test structure.

Packaged integrated circuit devices include an oscillator circuit having a resonator (e.g., quartz crystal, MEMs, etc.) associated therewith, which is configured to generate a periodic reference signal. A built-in self-test (BIST) circuit is provided, which is selectively electrically coupled to first and second terminals of the resonator during an operation by the BIST circuit to test at least one performance characteristic of the resonator, such as at least one failure mode. These test operations may occur during a built-in self-test time interval when the oscillator circuit is at least partially disabled. In this manner, built-in self-test circuitry may be utilized to provide an efficient means of testing a resonating element/structure using circuitry that is integrated within an oscillator chip and within a wafer-level chip-scale package (WLCSP) containing the resonator.