A method for automatically cleaning a probe card includes the following operations. A first wafer is tested in a chamber of a testing machine. A yield of the first wafer is monitored by a tool online monitor system (TOMS). An instruction file is transmitted by the TOMS to a tester, in which the instruction file compiles a first program code of the TOMS into a second program code of the tester. The second program code of the tester is received by the tester. A general purpose interface bus (GPIB) command is transferred to a testing machine by the tester. A cleaning operation is performed by the testing machine.

An inspection apparatus includes a light sensor that detects light from a semiconductor device to which an electric signal has been input, an optical system that guides light from the semiconductor device to the light sensor, and a control device electrically connected to the light sensor. The control device includes a measurement unit that acquires waveform data obtained by optical measurement for each of a plurality of positions on a defective semiconductor device and waveform data obtained by the optical measurement for each of a plurality of positions on a non-defective semiconductor device, a calculation unit that calculates a degree of correspondence between the waveform data of the defective semiconductor device and the waveform data of the non-defective semiconductor device, and an analysis unit that analyzes a defective part of the defective semiconductor device on the basis of the degree of correspondence for each of the plurality of positions.

A gettering property evaluation apparatus includes a gettering determination unit and a chuck table. The gettering determination unit has a laser beam applying unit for applying a laser beam to a wafer, and a transmission-reception unit for applying a microwave to the wafer and receiving the microwave reflected by the wafer. The gettering determination unit determines whether or not a gettering layer including a grinding strain generated by grinding the wafer has a gettering property. The chuck table holds the wafer on a holding surface. The chuck table has a conductive nonmetallic porous member constituting the holding surface and having a property of reflecting or absorbing the microwave, and a base member provided with a negative pressure transmission passage for transmitting a negative pressure to the nonmetallic porous member.

As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.

A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight oiler nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.

Herein disclosed are a wafer, a wafer testing system, and a method thereof. Said wafer testing method comprises the following steps. First, an incident light is provided toward a wafer. And, a wafer surface image corresponded to the wafer is generated. Then, determining whether the wafer surface image has a plurality of first strips and a plurality of second strips, and the plurality of first strips and the plurality of second strips are symmetrical. When the wafer surface image has the plurality of first strips and the plurality of second strips, and the plurality of first strips and the plurality of second strips are symmetrical, a qualified signal corresponded to the wafer is provided.

A test and measurement circuit including a capacitor in parallel with a device under test, a direct current voltage source configured to charge the capacitor, a pulse generator configured to generate a pulse for testing the device under test, and a sensor for determining a current in the device under test.

A board-like connector, a dual-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-arm bridges spaced apart from each other and an insulating layer. Each of the dual-arm bridges includes a carrier, a first cantilever, a second cantilever, a first abutting column, and a second abutting column, the latter two of which extend from the first and second cantilevers along two opposite directions. The first cantilever and the second cantilever extend from and are coplanar with the carrier. The insulating layer connects the carriers of the dual-arm bridges. The first abutting column and second abutting column of each of the dual-arm bridges respectively protrude from two opposite sides of the insulating layer, and are configured to abut against two boards, respectively.

The present disclosure provides an electrical test structure, a semiconductor structure and an electrical test method. In the electrical test structure, in a first direction, the electrical test structure includes a first layer, an interconnect hole and a second layer arranged in a stack, and the interconnect hole is in contact with the first layer; the second layer includes a body part and a test part, and the test part is connected to the body part; the interconnect hole is configured as, when an offset distance of the interconnect hole relative to a preset position in a second direction is less than a first preset distance, or an offset distance of the interconnect hole relative to the preset position in a third direction is less than a second preset distance, the interconnect hole is spaced apart from the test part.

A terahertz device includes an antenna base including reflective films, wherein: the reflective films are curved to be recessed; the reflective film and the reflective film are arranged to be adjacent to each other in a y direction; and when viewed from a z direction, the sizes of the reflective film and the reflective film along an x direction are smaller than the sizes of the reflective film and the reflective film along the y direction.