Patent classifications
G01R31/2834
METHOD AND APPARATUS FOR CONFIGURING SUB ROUTE FLOW, STORAGE MEDIUM, AND EQUIPMENT
A sub route flow is a route flow different from a main route flow in testing of a semiconductor product. A method for configuring a sub route flow includes: determining at least one test item of the semiconductor product; obtaining a first test template corresponding to the test item, wherein the first test template includes preset test parameters; displaying the preset test parameters; receiving test parameters adjusted according to the preset test parameters; configuring current test parameters of the test item according to the adjusted test parameters; and forming the sub route flow of the semiconductor product according to the current test parameters of the test item.
TESTING AN ELECTRONIC CIRCUIT HAVING A VOLTAGE MONITOR CIRCUIT
A system for testing is provided. The system includes an electronic circuit and an automatic testing equipment (ATE). The electronic circuit includes a voltage monitor including a resistive divider receiving at its voltage input an input voltage and coupled at its output to an input of a comparator. A reference input of the comparator is coupled to a generator supplying a reference voltage setting one or more thresholds of the comparator. The electronic circuit includes a Built In Self Test Module coupled to the ATE and to the inputs and output of the comparator. The BIST module is being configured upon receiving respective commands from the ATE to test a reaction time of the comparator and an offset of the comparator. The ATE performs a respective test of the ratio of the resistor divider by a first voltage measurement and a test of the reference voltage provided by the generator.
METHODS AND DEVICES FOR TESTING A DEVICE UNDER TEST USING TEST SITE SPECIFIC THERMAL CONTROL SIGNALING
Embodiments of the present invention provide an automated test equipment (a “tester”) for testing a device under test, including a bidirectional dedicated real-time handler interface. Some embodiments include an interface having a trigger function, a fixed endpoint interface, an interface arranged on a test head, and/or a number of lines/communication channels adapted to a specific communication task, without separate signal lines, for example. The bidirectional dedicated real-time handler interface can be used to transmit thermal control signals, and the transmitted signals can be test site specific. The real-time signaling advantageously improves testing accuracy and efficiency.
COMPARATOR WITH CONFIGURABLE OPERATING MODES
A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.
Systems and methods for ground fault detection
A ground fault detection circuit can include a band-pass filter that can have a first node and a second node that can be coupled to an earth ground. The first node can be coupled to a local ground of an automatic test equipment (ATE) system for an electrical device that can be coupled via at least one wire to the ATE. The band-pass filter can be configured to pass and amplify a test current signal established at the first node in response to a coupling of one of a conductor of the at least one wire carrying the test current signal to the local ground, and a conductive element of the electrical device carrying the test current signal to the local ground. A fault alert signal can be provided to provide an indication of ground fault based on a comparison of the amplified test current signal.
Multiple circuit board tester
The present invention is directed to a system for testing printed circuit boards. The system is configured to test the simultaneously test a multiplicity of printed circuit boards. The system examines the electrical characteristics of a printed circuit board and is operable to identify if a printed circuit board meets a desired characteristic.
VECTOR NETWORK ANALYZER WITH DIGITAL INTERFACE
A measuring device includes a first measuring port connected to an optical interface which can be connected to an optical input or output of a device under test (DUT). The device includes a second measuring port which can be connected to a radio frequency (RF) input or output of the DUT. The optical interface is connected to the optical input of the DUT and the second measuring port is connected to the RF output of the DUT. The first measuring port generates an analog measuring signal and provides it to the optical interface. The optical interface generates an optical measuring signal based on the analog measuring signal and provides it to the optical input of the DUT. The second measuring port receives an analog measuring signal generated by the DUT based on the optical measuring signal. The processor determines S-parameters of the DUT based on the two analog measuring signals.
SCAN CHAIN DESIGNING AND CIRCUIT TESTING METHOD
A scan chain designing method includes: obtaining test points according to a gate-level netlist; determining integers M and N, wherein M and N are no greater than an amount X of the test points; selecting M and N test points to be a first and second set test points according to a priority; obtaining a first test coverage and a first test pattern count according to the first set test points and obtaining a second test coverage and a second test pattern count according to the second set test points; obtaining a predicted test coverage curve according to the first and second test coverages; determining an optimum amount O according to the predicted test coverage curve, the first and second test pattern counts, wherein O is no greater than X; and selecting O test points to arrange a scan chain according to the priority and the optimum amount O.
Dynamically determining measurement uncertainty (MU) of measurement devices
A method is provided for dynamically determining measurement uncertainty (MU) of a measurement device for measuring a signal output by a device under test (DUT). The method includes storing characterized test data in a nonvolatile memory in the measurement device, the characterized test data being specific to the measurement device for a plurality of sources of uncertainty; receiving a parameter value of the DUT; measuring the signal output by the DUT and received by the measurement device; and calculating the measurement uncertainty of the measurement device for measuring the received signal using the stored characterized test data and the received parameter value of the DUT.
Power supply, automated test equipment, method for operating a power supply, method for operating an automated test equipment and computer program using a voltage variation
A power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is triggered in response to an expected load change. An Automated test equipment for testing a device under test comprises a power supply, which is configured to supply the device under test. The automated test equipment comprises a pattern generator configured to provide one or more stimulus signals for the device under test. The power supply is configured to perform an at least partial compensation of a voltage variation caused by a load change using a voltage variation compensation mechanism which is activated in synchronism with one or more of the stimulus signals and/or in response to one or more response data signals from the device under test. Corresponding methods and a computer program are also described.