A light emitting element driving semiconductor integrated circuit constitutes at least a part of a light emitting element driving device arranged to drive a series connection unit including a plurality of light emitting elements. The light emitting element driving semiconductor integrated circuit includes a single-element short-circuit detection unit arranged to detect that one of the plurality of light emitting elements is short-circuited, and a control unit arranged to control a power element of the light emitting element driving device so that current supplied from the light emitting element driving device to the series connection unit is increased, when the single-element short-circuit detection circuit detects that one of the plurality of light emitting elements is short-circuited.

A method for diagnosing an electrical circuit including at least one electrical device, an actuator for the device controlled by a high side actuating switch and a low side actuating switch, and at least one additional switch not in series with any of the HS or LS switch, the method including: to each of the possible statuses of the circuit, giving a code; sequentially putting the circuit in at least some of these statuses for a given time period; during each of these periods, measuring voltage and/or current in different parts of the circuit and giving a code to the measurement; and establishing a diagnosis of correct functioning or of a malfunctioning of at least some elements of the circuit according to a pre-established correlation between the status codes and the measurement codes.

Packaged integrated circuit devices include an oscillator circuit having a resonator (e.g., quartz crystal, MEMs, etc.) associated therewith, which is configured to generate a periodic reference signal. A built-in self-test (BIST) circuit is provided, which is selectively electrically coupled to first and second terminals of the resonator during an operation by the BIST circuit to test at least one performance characteristic of the resonator, such as at least one failure mode. These test operations may occur during a built-in self-test time interval when the oscillator circuit is at least partially disabled. In this manner, built-in self-test circuitry may be utilized to provide an efficient means of testing a resonating element/structure using circuitry that is integrated within an oscillator chip and within a wafer-level chip-scale package (WLCSP) containing the resonator.

A negative voltage testing including a monitoring and triggering circuit coupled to a supply voltage rail of a device under test (DUT) and a switching circuit coupled to the monitoring and triggering circuit. The monitoring and triggering circuit is configured to cause the switching circuit to provide a first negative voltage to the supply voltage rail when a supply voltage on the supply voltage rail decays below a predetermined level during a first test of the DUT.

A method, including determining a change in an actuator impedance based on a change in an electrical property of a system of which the actuator is apart, and determining one or more system characteristics based on the change in the actuator impedance.

A load estimating device measures a voltage and a current supplied to a load connected with a generator, calculates a feature amount of the load, senses a remaining amount of fuel, outputs a time during which the load is continuously operable. The device estimates what the load connected with the generator is, based on the calculated feature amount and the feature amounts stored in a storage, and determines the time during which the estimated load is continuously operable, based on a power consumption of the estimated load, and the remaining amount of fuel. The device has a load registration mode for causing the storage to store therein a feature amount of a new load that is not stored in a storage.

Accordingly, an improved interposer connection testing technique is provided, employing parallel pseudo-random bit sequence (PRBS) generators to test all the interconnects in parallel and simultaneously detect any correctable defects. In one embodiment, a microelectronic assembly includes an interposer electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die, the substrate having multiple conductive traces for a parallel communications bus between the IC dies. The originating IC die has a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the interposer traces. The destination IC die has a second parallel PRBS generator to create reference PRBSs with different phases, and a bitwise comparator coupled to receive the test PRBSs from the interposer traces and to compare them to the reference PRBSs to provide concurrent fault monitoring for each of the traces.

An abnormality prompting method and an intelligent socket (30) are provided. Prompting is performed when a home appliance runs abnormally by means of the intelligent socket (30). The method includes: the intelligent socket (30) receives a state message from a first home appliance (S202), and the state message includes indication information used for indicating a current working mode of the first home appliance; the intelligent socket (30) obtains an actual value of a working parameter of the first home appliance (S203); the intelligent socket (30) determines a working state of the first home appliance according to the actual value of the working parameter and a maximum value of the working parameter allowed by the working mode (S204); when determining that the working state of the first home appliance is an abnormal state, the intelligent socket (30) outputs a prompt message (S205).

A display device including: a substrate including a display area and a peripheral area peripheral to the display area; a plurality of pads disposed in a pad area, wherein the pad area is disposed in the peripheral area and the pad area includes an integrated circuit (IC); and a first crack detecting line connected to a first pad and a second pad at a first node, and a third pad at a second node, wherein the first crack detecting line is disposed in the peripheral area between the first node and the second node.

A method, including determining a change in an actuator impedance based on a change in an electrical property of a system of which the actuator is apart, and determining one or more system characteristics based on the change in the actuator impedance.