A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.

A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.

A test method for testing connectivity of a semiconductor structure includes operations as follows. A semiconductor structure and a detection transistor are provided. The semiconductor structure includes a through silicon via structure having a first terminal and a second terminal arranged to be opposite. An intrinsic conductivity factor of the detection transistor is obtained. The detection transistor is turned on upon receiving a test signal, and a test voltage is provided to the second terminal, to enable the detection transistor to operate in a deep triode region, and a current flowing through the second terminal is obtained during operation of the detection transistor in the deep triode region. A resistance of the through silicon via structure is obtained based on the intrinsic conductivity factor, an operating voltage, the test voltage, and the current flowing through the second terminal.

The present disclosure provides a method and an apparatus of testing a circuit, and a storage medium. The method of testing a circuit includes: determining a preset circuit module in a to-be-tested circuit and a preset node in the preset circuit module; inputting a test signal to an input terminal of the to-be-tested circuit according to a preset input rule, and obtaining a signal of the preset node in the preset circuit module; and determining a status of the preset circuit module based on the obtained signal of the preset node.

A test method for testing connectivity of a semiconductor structure includes operations as follows. A semiconductor structure and a detection transistor are provided. The semiconductor structure includes a through silicon via structure having a first terminal and a second terminal arranged to be opposite. An intrinsic conductivity factor of the detection transistor is obtained. The detection transistor is turned on upon receiving a test signal, and a test voltage is provided to the second terminal, to enable the detection transistor to operate in a deep triode region, and a current flowing through the second terminal is obtained during operation of the detection transistor in the deep triode region. A resistance of the through silicon via structure is obtained based on the intrinsic conductivity factor, an operating voltage, the test voltage, and the current flowing through the second terminal.

A method for identifying a latch-up structure includes the following: in a chip layout, a first N-type heavily doped region connected to a first input/output pad and located in a P-type substrate is found; a first P-type heavily doped region located in an N-well and a second P-type heavily doped region located in the P-type substrate, both of which are adjacent to the first N-type heavily doped region, are found; a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the N-well is found, wherein the N-well is located on the P-type substrate; and an area formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well and the P-type substrate is identified as the latch-up structure.

In a general aspect, a wire bonding apparatus can include a supply of bond wire, a wire bonding head, and an electrical continuity tester. The wire bonding head can including a wire cutter. The wire cutter can be electrically conductive. The electrical continuity tester can be coupled between the supply of bond wire and the wire cutter.

Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

A self-test system for PCIe and a method thereof are disclosed. In the system, a first circuit interconnect card and a second circuit interconnect card are inserted into CEM slots, respectively, and the first circuit interconnect card and the second circuit interconnect card are electrically connected to each other through a FFC, the central processing unit generates and provides differential signals to the first circuit interconnect card and the second circuit interconnect card; the first circuit interconnect card or the second circuit interconnect card provide differential signals to the second circuit interconnect card or the first circuit interconnect card through the first FFC interface and the second FFC interface, respectively, and the second circuit interconnect card or the first circuit interconnect card provides the differential signals to a central processing unit, so as to implement self-check for PCIe.

An integrated circuit comprises a substrate that includes a first surface and a second surface. A first through substrate via (TSV) is formed between the first surface and the second surface and a first conductive material is arranged within the first TSV to form a conductive path between the first surface and the second surface through the substrate. A second TSV is formed between the first surface and the second surface and a second conductive material arranged within the second TSV to form a conductive path between the first surface and the second surface through the substrate. In examples the first TSV has a larger cross-sectional area than the second TSV, the cross-section of the first TSV and second TSV being in a plane parallel to the first surface or the second surface.