A reduced pin count (RPC) device includes an electrical circuitry in a package with uniformly distributed leads, a subset of the leads being electrically disconnected form the circuitry. A contactor pin block with sockets corresponding to the uniformly distributed leads has the sockets corresponding to the leads with electrical connections filled with test pins suitable for contacting respective leads, and the sockets corresponding to the electrically disconnected leads voided of test pins. Dummy plugs are inserted into the voided sockets to block the sockets and prevent accidental insertions of test pins.

A wafer inspection device 10 is provided with a chuck top 20 on which a wafer W having semiconductor devices formed thereon is placed, a probe card 18 having multiple contact probes 28 protruding toward the wafer W, a pogo frame 23 for holding the probe card 18, a cylindrical internal bellows 26 configured to suspend from the pogo frame 23 to surround the contact probes 28, and a cylindrical external bellows 27 configured to suspend from the pogo frame 23 to surround the internal bellows 26. When the chuck top 20 approaches the probe card 18 and the contact probes 28 are brought into contact with the devices, the internal bellows 26 and the external bellows 27 come in contact with the chuck top 20, a sealing space P is formed between the internal bellows 26 and the external bellows 27, and the sealing space P is compressed.

Limiting circuitry is disclosed. In one example, the limiting circuitry provides limited electric current and/or limited electric voltage for electrically testing at least one device under test. The limiting circuitry comprises a plurality of DC-DC-converters being connected in parallel to each other, each being provided with an electric input DC voltage and each being configured for providing a converted electric output current to be forwarded to an assigned one of electric contacts for contacting the at least one device under test. A control mechanism is configured for controlling the DC-DC-converters for limiting the electric output current and/or an electric output voltage which relates to said electric output current.

A margin tester including an identification reader configured to receive an adaptor identifier of an adaptor, an interface configured to connect to a device under test through the adaptor, and one or more processors configured to assess a margin, such as an electrical margin or an optical margin, of a device under test and tag the assessment with the adaptor identifier. Assessing the margin can include assessing the margin based on an expected margin that is predicted or provided based on the adaptor identifier.

An integrated circuit, a crack status detector and a crack status detection method are provided. The crack status detector includes a detection ring, multiple switches, and a current measuring circuit. The detection ring is formed by multiple conductive wire segments coupled in series. The detection ring is disposed adjacent to a side of at least one guard ring in the integrated circuit. The detection ring has a first endpoint and a second endpoint to respectively receive a first reference voltage and a second reference voltage. Each of the switches is disposed between two adjacent conductive wire segments. The switches are respectively turned on or cut off according to multiple control signals. The current measuring circuit transmits the control signals and measures a current on the detection ring according to a turned-on or cut-off status of each of the switches, so as to detect a crack status of the integrated circuit.

A wafer inspection device 10 is provided with a chuck top 20 on which a wafer W having semiconductor devices formed thereon is placed, a probe card 18 having multiple contact probes 28 protruding toward the wafer W, a pogo frame 23 for holding the probe card 18, a cylindrical internal bellows 26 configured to suspend from the pogo frame 23 to surround the contact probes 28, and a cylindrical external bellows 27 configured to suspend from the pogo frame 23 to surround the internal bellows 26. When the chuck top 20 approaches the probe card 18 and the contact probes 28 are brought into contact with the devices, the internal bellows 26 and the external bellows 27 come in contact with the chuck top 20, a sealing space P is formed between the internal bellows 26 and the external bellows 27, and the sealing space P is compressed.

A method and apparatus for controlling a tester, related medium and electronic device are provided. The apparatus includes a vibration data collector attached on a side wall of the tester to collect vibration data from the tester during operation thereof. The method includes: receiving the vibration data collected by the vibration data collector; comparing the vibration data with a predetermined threshold to generate a comparison result; and controlling an operating state of the tester based on the comparison result. This method may timely identify any instability of the tester and prompt for repair if necessary. It substantially reduces the time and material costs associated with a test, and thus reduces the non-chip-attributable defect rate.

A method and apparatus for controlling a tester, related medium and electronic device are provided. The apparatus includes a vibration data collector attached on a side wall of the tester to collect vibration data from the tester during operation thereof. The method includes: receiving the vibration data collected by the vibration data collector; comparing the vibration data with a predetermined threshold to generate a comparison result; and controlling an operating state of the tester based on the comparison result. This method may timely identify any instability of the tester and prompt for repair if necessary. It substantially reduces the time and material costs associated with a test, and thus reduces the non-chip-attributable defect rate.

A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.

Apparatuses of a noise measurement system and methods for using the same are disclosed. In one embodiment, a noise measurement system may include a plurality of probe groups electrically coupled to a plurality of DUTs, where a probe group in the plurality of probe groups includes multiple channels, and where the multiple channels of each probe group are bundled as a group for reducing electromagnetic interference among the plurality of probe groups, and wherein the group is shielded from corresponding signal groups of other DUTs with a connection to a circuit ground of the noise measurement system for reducing ground loop generated signal interference. The noise measurement system may further include a controller configured to perform noise measurement.