The invention relates to a method as well as an apparatus configured for its execution for monitoring the reliability of an electronic system, in particular an electronic system comprising one or more electronic components. The method comprises: repeatedly measuring, at different measurement times and according to a predetermined transmission quality measure, a transmission quality of signals transmitted to or from the electronic system over a wired electrical signal transmission path; (ii) comparing, for each of the measurement times, the associated measured transmission quality with a respective associated transmission quality reference value previously determined according to the transmission quality measure; and (iii) determining a value of a reliability indicator associated with the respective measurement time in dependence on the result of the associated comparison In this regard, the transmission quality measure is defined as a measure of the extent of a subrange of a one- or multi-dimensional operating parameter range of the electronic system in which, according to a predetermined reliability criterion, the electronic system operates reliably.

A chip testing method and apparatus, and an electronic equipment are provided. The method includes: determining, according to pad distribution information of a target chip, positions of set state pads and positions of non-set state pads in the target chip, the set state pads being pads with set states, and the set states including a first state or a second state; determining a plurality of pad state setting schemes according to the positions of the set state pads and the positions of the non-set state pads, the pad state setting schemes including setting each of the non-set state pads to the first state or the second state; and determining a test voltage setting scheme satisfying a preset condition according to information of differential voltage pad pairs in each of the pad state setting schemes, the differential voltage pad pair comprising two adjacent pads in different states.

A system, a method, and a machine-readable medium for overclocking a computer system is provided. An example of a method for overclocking a computer system includes predicting a stable operating frequency for a central processing unit (CPU) in a target system based, at least in part, on a model generated from data collected for a test system. An operating frequency for the CPU is adjusted to the stable operating frequency. A benchmark test is run to confirm that the CPU is operating within limits.

Systems and methods are disclosed for IC fabrication by specifying a process monitor with one or more functional blocks including process monitoring structures and wafer identification and die location data on the wafer; fabricating the functional blocks embedded in the wafer at one or more die locations; capturing functional test measurements during or after fabricating the functional blocks; and predicting device failures based on information of known device failures or related process parameters and their relationship to functional test measurements.

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system comprises pre-qualifying test components, functional test components, a controller, a transceiver, and a switch. The pre-qualifying test components are configured to perform pre-qualifying testing on a device under test. The functional test components are configured to perform functional testing on the device under test. The controller is configured to direct selection between the pre-qualifying testing and functional testing. The transceiver is configured to transmit and receive signals to/from the device under test. The switch is configured to selectively couple the transceiver to the pre-qualifying test components and functional test components.

Various embodiments of the present invention relate to a method for detecting and controlling a battery status by using a sensor, and an electronic device using the same, the electronic device comprising: a housing; an accommodation part arranged inside the housing and including at least one gas sensor; a battery arranged inside the housing; a memory for storing information, acquired by the at least one gas sensor, on gas leaked from the battery and operation control information of the electronic device; and a processor electrically connected to the memory, wherein the processor is configured to acquire a detection signal of gas leaked from the battery by using the at least one gas sensor, and control the operation of at least a part of the electronic device and/or charging characteristics of the battery when the acquired gas detection signal exceeds a predetermined threshold value, so as to detect, in real time, a gas leakage of the battery occurring because of the exposure of the electronic device to high temperature or heat generation and control the battery status, thereby preventing safety accidents caused by the battery. Other various embodiments in addition to the disclosed various embodiments in the present invention are possible.

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

Disclosed are a method, device and system for health monitoring of SoC. The method includes: acquiring in real time sensor data of sensors monitoring SoC performance, the sensor data including reliability degradation sensor data, temperature sensor data, noise sensor data and current sensor data; extracting characteristic data representative of the SoC performance from the sensor data; performing analysis and prediction on the characteristic data in real time by using a prediction algorithm to obtain a performance state and a performance degradation trend of the SoC; outputting performance state information and performance degradation trend information of the SoC. The disclosed method, device and system for health monitoring of SoC can monitor the performance state of the SoC in real time and predict the performance degradation trend of the SoC in real time.

A circuit includes one or more sensors formed on one or more dies, each sensor detecting one or more wafer characterization data; a stress generator on the die to control the one or more sensors to place the one or more sensors under stress during wafer manufacturing or operation; and an interface coupled to the one or more sensors to communicate the wafer characterization data to a processor or a tester.