The subject disclosure relates to a system and method for testing units-under-test (UUT) with a thermal shock. The thermal shock testing system can include a chamber having an inlet and an outlet, the chamber being configured to provide a thermal shock to a unit-under-test (UUT), a pump configured to fluidly connect to the inlet of the chamber and direct a temperature controlled liquid through a channel embedded in the chamber, and a boiler and a chiller fluidly connected to the pump, the temperature of the liquid being controlled by at least one valve configured to alternatively direct hot or cold fluid to the inlet of the chamber.

The disclosure describes to techniques for detecting field failures or performance degradation of circuits, including integrated circuits (IC), by including additional contacts, i.e. terminals, along with the functional contacts that used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, temperature and impedance. These electrical characteristics may be representative of a certain failure mode and may be an indicator for circuit state-of-health (SOH), while the circuit is performing in the field.

Controlling of drop test equipment. A predefined test script is obtained over a machine-machine interface. The test script comprises plurality of test settings for drop testing of a device-under-test, DUT. The drop test equipment is controlled to perform drop testing of the DUT according to the test settings of the test script. Test results are collected and provided to a test report.

The subject disclosure relates to a system and method for testing units-under-test (UUT) with a thermal shock. The thermal shock testing system can include a chamber having an inlet and an outlet, the chamber being configured to provide a thermal shock to a unit-under-test (UUT), a pump configured to fluidly connect to the inlet of the chamber and direct a temperature controlled liquid through a channel embedded in the chamber, and a boiler and a chiller fluidly connected to the pump, the temperature of the liquid being controlled by at least one valve configured to alternatively direct hot or cold fluid to the inlet of the chamber.

A test circuit includes one or more sensors adapted to be formed on a wafer, each sensor detecting one or more wafer characterization data in a stressed condition; a stress generator controlling the one or more sensors to place the one or more sensors under stress during wafer manufacturing; memory coupled to the one or more sensors to store wafer characteristics under the stressed condition; and an interface coupled to the memory to communicate the wafer characterization data to a tester.

Systems, methods, and computer program products for virtual machine testing of an electric machine (8). A test signature including parameter values measured during one or more static tests of the electric machine (8) is compared to a reference signature generated by performing a similar series of static tests on a reference machine (42). The reference machine (42) is then validated by subjecting the reference machine to full-load dynamic testing. The test and reference signatures may include a plurality of parameters each characterizing a physical property of the respective machines (8, 42) in one or more physical domains The parameters are selected so that the electric machine (8) can be qualified for operation in the field by comparing the test signature to the reference signature, thereby avoiding the need for full-load dynamic testing of the electric machine (8).

A semiconductor package test apparatus is provided. A semiconductor package test apparatus comprises a test board including a plurality of sensors, a chamber into which the test board is loaded, and a controller configured to control a temperature of the chamber, wherein the controller adjusts the temperature using the plurality of sensors.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system comprises pre-qualifying test components, functional test components, a controller, a transceiver, and a switch. The pre-qualifying test components are configured to perform pre-qualifying testing on a device under test. The functional test components are configured to perform functional testing on the device under test. The controller is configured to direct selection between the pre-qualifying testing and functional testing. The transceiver is configured to transmit and receive signals to/from the device under test. The switch is configured to selectively couple the transceiver to the pre-qualifying test components and functional test components.

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

An integrated circuit includes at least one first magnetic field sensing element including at least one first magnetoresistance element configured to provide an output signal of the integrated circuit in response to a detected magnetic field. The integrated circuit also includes at least one second magnetic field sensing element including at least one second magnetoresistance element configured to have a characteristic indicative of a stress condition. A method for detecting a stress condition in an integrated circuit is also provided.