A method of inspecting a sensor including generating a first model based on first big-data including first inspection results for sensors of a same type connected to a current inspection environment, generating first target characteristic coefficients for channels included in the first model, generating first characteristic coefficients for channels included in a current sensor, and generating first compensation coefficients for the channels included in the current sensor based on the first target characteristic coefficients and the first characteristic coefficients.

A method for determining an emission coefficient of a device under test (DUT) using a test circuit comprises coupling a parameter measurement circuit associated with the test circuit to an input pin associated with the DUT, wherein the input pin is coupled to a diode element within the DUT and performing voltage and current measurements associated with the input pin using the parameter measurement circuit. In some embodiments, the method further comprises determining a plurality of contact resistance values respectively based on the voltage and current measurements and an emission coefficient estimate using a contact resistance estimation circuit; and determining an emission coefficient associated with the DUT based on the determined plurality of contact resistance values using an emission coefficient determination circuit.

A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die.

The present disclosure provides an electrical test structure, a semiconductor structure and an electrical test method. In the electrical test structure, in a first direction, the electrical test structure includes a first layer, an interconnect hole and a second layer arranged in a stack, and the interconnect hole is in contact with the first layer; the second layer includes a body part and a test part, and the test part is connected to the body part; the interconnect hole is configured as, when an offset distance of the interconnect hole relative to a preset position in a second direction is less than a first preset distance, or an offset distance of the interconnect hole relative to the preset position in a third direction is less than a second preset distance, the interconnect hole is spaced apart from the test part.

A method and a testing apparatus related to wafer testing are provided. In the method, testing raw data is obtained by a testing apparatus operating with a Unix-related system. The testing raw data is a testing result of probe testing on one or more wafers by the testing apparatus. The testing raw data is converted into converted data by the testing apparatus. The converted data is related to the defect information of the wafer. Analyzed data is generated by the testing apparatus according to the converted data. The analyzed data is used for a graphical interface. Therefore, real-time defect analysis during the testing procedure may be provided.

An illuminator system for semiconductor chip testing has a rotary plate and a first light source and second light source mounted on the rotary plate. A controller is configured to rotate the rotary plate to provide a desired light output. A light output of the illuminator system is aligned to the desired first or second light source. A first semiconductor chip receives illumination from the desired source. The rotary plate is rotated until the desired light source is aligned to the light output. A quality or characteristic of light emitted by the first light source can be measured, and then the first light source can be adjusted, or an alert can be generated, if the quality or characteristic falls outside of a preconfigured range.

The present disclosure provides a process variation detection circuit and a process variation detection method. The process variation detection circuit is arranged in a chip and includes: a first ring oscillator, where a first number of auxiliary elements of a preset type are arranged between two adjacent inverters of the first ring oscillator; and a second ring oscillator, where a second number of auxiliary elements of a preset type are arranged between two adjacent inverters of the second ring oscillator, the second number is larger than the first number; wherein, a number of the inverter of the first ring oscillator is the same as a number of the inverter of the second ring oscillator; a type and a size of a transistor of the first ring oscillator are the same as a type and a size of a transistor of the second ring oscillator.

The present disclosure provides a process corner detection circuit and a process corner detection method. The process corner detection circuit includes: M ring oscillators disposed inside a chip, M≥1, where types of N-type transistors in the M ring oscillators are not exactly the same, and types of P-type transistors in the M ring oscillators are not exactly the same; transistor types of the M ring oscillators include all transistor types used in the chip; the ring oscillators include symmetric ring oscillators and asymmetric ring oscillators; types of N-type transistors and P-type transistors in the symmetric ring oscillators are the same; and types of N-type transistors and P-type transistors in the asymmetric ring oscillators are different.

A method and system for evaluating test data, a wafer test system, and a storage medium are provided. The method for evaluating test data includes: obtaining test data of a plurality of test programs, each test program including a plurality of test items; for each test program, calculating a correlation coefficient of each test item according to the test data; drawing a difference analysis graph for every two test programs in the plurality of test programs according to the correlation coefficient between each of the test items in different test programs, where a horizontal axis and a longitudinal axis of the difference analysis graph respectively correspond to one test program; and evaluating a difference of each test item in two different test programs according to the difference analysis graph.

A method for monitoring defects of a product implemented in an electronic device obtains product data in real time and determines whether a product is defective based on the product data; when the product is defective, outputting first warning information based on the number of defects of the product which satisfy a first preset condition; obtaining a rate of defects of the product every first preset time period, and outputting second warning information based on the rate of defects of the product when the rate of defects satisfies at least one of a second, third, and fourth preset conditions; when any warning information is output, analyzing distribution of the defects of the product; and predicting at least one cause of each defect of the product according to historical maintenance data of the product and a self-learning record of the electronic device.