An apparatus and a method for inspecting a semiconductor includes a water tank which includes a housing, an interior of which is filled with a liquid, and a support block which provides a settling surface for an inspection object inside the housing. A plurality of signal generators are installed on a bottom surface of the housing, and output a frequency signal in a direction in which the inspection object is located. A power supply operates the signal generators. A probe is placed above the inspection object, and a receiver which operates with the probe and is attached to a bottom surface of the support block. Foreign matter remaining on the inspection object are removed, using a plurality of frequency signals which are output by the plurality of signal generating units.

A cleaning method in an inspection apparatus that performs an electrical characteristic inspection on a device under test formed in an inspection object, includes: transferring, in a transfer process, a stage on which the inspection object is mounted to a position facing a probe card having probes, the probes being brought into contact with the device under test during the electrical characteristic inspection; subsequently, exhausting and depressurizing a space between the probe card and the stage facing the probe card in a peeling-off preparation process; introducing a gas into the space which has been depressurized and peeling off foreign substances adhering to a front surface of the stage and the probes in a foreign substance peeling-off process; and exhausting the space to discharge the foreign substances while continuously introducing the gas into the space in a foreign substance discharging process.

Methods and apparatus of forming a thermal interface with condensate are described. In an example, a device may be disposed in a test environment or a test apparatus. An amount of condensate may be accumulated on a heat sink to coat the heat sink with a layer of condensate. The coated heat sink may be disposed on the device, where the layer of condensate is directed towards the device, and the disposal of the coated heat sink causes the layer of condensate to spread among voids between the heat sink and the device to form a thermal interface that includes the condensate. A test may be executed on the device with the thermal interface comprising the condensate between the coated heat sink and the device.

Described herein are a system and method of preparing integrated circuits (ICs) so that the ICs remain electrically active and can have their active circuitry probed for diagnostic and characterization purposes using charged particle beams. The system employs an infrared camera capable of looking through the silicon substrate of the ICs to image electrical circuits therein, a focused ion beam system that can both image the IC and selectively remove substrate material from the IC, a scanning electron microscope that can both image structures on the IC and measure voltage contrast signals from active circuits on the IC, and a means of extracting heat generated by the active IC. The method uses the system to identify the region of the IC to be probed, and to selectively remove all substrate material over the region to be probed using ion bombardment, and further identifies endpoint detection means of milling to the required depth so as to observe electrical states and waveforms on the active IC.

A method of designing a robust integrated circuit that is not vulnerable to optical fault injection comprises training a variational autoencoder to identify regions in a target integrated circuit that are vulnerable to optical fault injection and altering the design of the target integrated circuit by altering the design of the vulnerable regions so that the target integrated circuit is no longer vulnerable to optical fault injection, thereby forming the robust integrated circuit.

Provided is a die extraction method, comprising the following steps: removing solder balls; polishing a front side of the sample to remove a part on a front side of the target die, and retain a part of a die attach film (DAF) layer on the front side of the target die and a bonding wire located in the part; attaching the front side of the sample to the polishing jig and flattening the sample and the polishing jig by the flattener; polishing the back side of the sample to remove a part on a back side of the target die, and retain a DAF layer on the back side of the target die; removing the DAF and a packaging material remaining on the sample to obtain the target die; and attaching the back side of the target die to a glass slide, thus completing extraction of the target die.

A probe head that contains a coining surface and a plurality of probe tips integrated on a same side of the probe head is provided. The probe head has a first portion and a laterally adjacent second portion, wherein the first portion of the probe head contains the coining surface, and the second portion of the probe head contains the plurality of the probe tips. Each probe tip may, in some embodiments, extend outwards from a probe pedestal that is in contact with the second portion of the probe head. The probe head is traversed across the surface of a semiconductor wafer containing a plurality of solder bump arrays such that the coining surface contacts a specific array of solder bumps prior to contacting of the same specific array of solder bumps with the probe tips.

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

Described are various embodiments of a contrast-enhancing staining system and method. In one embodiment, a method is described for enhancing contrast in an image of a substrate surface between regions of said substrate having different charge carrier characteristics. The method comprises exposing said substrate to a staining precursor comprising an oxidant; directing microwave electromagnetic radiation at the substrate, said microwave electromagnetic radiation enhancing a reaction rate of said oxidant reacting into a deposition material, said reaction rate being related to the charge carrier characteristics of a proximal region; and acquiring an image of said substrate surface indicating a visual contrast between each of said regions based on differential deposition of the deposition material therebetween.

The present invention discloses a method for preparing a semiconductor sample for failure analysis, which is characterized by using an adhesive layer comprising a non-volatile and non-liquid adhesive material with higher adhesion to the dielectric materials and lower adhesion to the metallic contact materials to selectively remove part of the dielectric materials in a large area with high uniformity, but completely remain the metallic contact materials, and not chemically react with the semiconductor specimens or even damage to the structures of interest to be analyzed, and different adhesive materials can be selected as the adhesive layer to control the adhesion to the dielectric layer, thereby the removed thickness of the dielectric layer can be controlled to provide a semiconductor specimen for failure analysis.