Detection circuitry for an integrated circuit (IC) includes voltage divider circuitry, comparison circuitry, and calibration circuitry. The voltage divider circuitry receives a power supply signal and output a first reference voltage signal and a supply voltage signal based on the power supply signal. The comparison circuitry compares the first reference voltage signal and the supply voltage signal to generate an output signal. The calibration circuitry alters one or more parameters of the voltage divider circuitry to increase a voltage value of the supply voltage signal based on the comparison of the first reference voltage signal with the supply voltage signal.

Electrostatic discharge (ESD) test systems include a FET-based pulse generator using pairs of back-to-back FETs coupled to produce an ESD pulse based on discharging a capacitor that is coupled in series with a device under test (DUT). A number of FETs can be selected based on an intended ESD test voltage magnitude.

A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.

The disclosed technology provides solutions for validating operation of a sensor assembly by performing an assembly test. In some aspects, a process of performing the assembly test includes steps for collecting motor controller measurements, wherein the motor controller measurements include an amount of current supplied to a motor coupled when performing a sensor sweep, calculating an average current drawn by the motor based on the current measurements, and calculating a peak current drawn by the motor based on the current measurements. In some aspects, the process can further include steps for determining if the sensor assembly passes the sensor assembly test based on the average current drawn and the peak current drawn. Systems and machine-readable media are also provided.

According to one embodiment, a multichannel switch integrated circuit (IC) includes a multichannel switch circuit and a common test terminal. The multichannel switch circuit includes a plurality of switch circuitries. Each of the switch circuitries includes: an output transistor that outputs an output signal through an output terminal; an overcurrent detection circuit that detects a detection current according to a current flowing through the output transistor; and a diode having an anode that receives the detection current. The common test terminal is connected to each channel switch circuitry, connected to the overcurrent detection circuit through the diode, and connected to a cathode of the diode.

Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector.

In various examples, permanent faults in hardware component(s) and/or connections to the hardware component(s) of a computing platform may be predicted before they occur using in-system testing. As a result of this prediction, one or more remedial actions may be determined to enhance the safety of the computing platform (e.g., an autonomous vehicle). A degradation rate of a performance characteristic associated with the hardware component may be determined, detected, and/or computed by monitoring values of performance characteristics over time using fault testing.

An abnormality detection method according to one aspect of the present disclosure is a method of detecting an abnormality in an AC signal to be input from an AC power supply. The method includes, where an ideal AC signal is represented as V.sub.0 sin ωt (V.sub.0: amplitude, co: angular frequency, t: time), calculating an arithmetic value including a value represented by sin.sup.2ωt+cos.sup.2ωt and determining that the AC signal is abnormal when the arithmetic value is out of a threshold range.

A test element group (TEG) disposed adjacent to at least one memory chip on a wafer includes a ring oscillator configured to output a clock signal based on a direct current (DC) signal received through a first pad and from a test device, a first divider configured to divide the clock signal and to output a first divided signal, and a sequential circuit set configured to receive the clock signal and the first divided signal, to generate a test signal based on the clock signal and the first divided signal, and to output the test signal to the test device through a second pad. The sequential circuit set includes a sequential circuit having a configuration corresponding to at least one circuit included in the at least one die.

Examples relate to a current sensor and to a method for sensing a strength of an electric current using two groups of magnetic sensing probes. The current sensor includes a first group and a second group of magnetic sensing probes. The current sensor comprises sensor circuitry coupled to the first and the second group of magnetic sensing probes. The sensor circuitry is configured to determine a first differential magnetic field measurement of a magnetic field using probes of the first group of magnetic sensing probes. The sensor circuitry is configured to determine a second differential magnetic field measurement of the magnetic field using probes of the second group of magnetic sensing probes. The sensor circuitry is configured to determine a strength of the electric current based on a difference between the first differential magnetic field measurement and the second differential magnetic field measurement.