Patent classifications
G01R31/3163
Method for diagnosing analog circuit fault based on vector-valued regularized kernel function approximation
A method for diagnosing analog circuit fault based on vector-valued regularized kernel function approximation, includes steps of: step (1) acquiring a fault response voltage signal of an analog circuit; step (2) carrying out wavelet packet transform on the collected signal, and calculating a wavelet packet coefficient energy value as a characteristic parameter; step (3) utilizing a quantum particle swarm optimization algorithm to optimize a regularization parameter and kernel parameter of vector-valued regularized kernel function approximation, and training a fault diagnosis model; and step (4) utilizing the trained diagnosis model to recognize circuit faults.
Method for diagnosing analog circuit fault based on vector-valued regularized kernel function approximation
A method for diagnosing analog circuit fault based on vector-valued regularized kernel function approximation, includes steps of: step (1) acquiring a fault response voltage signal of an analog circuit; step (2) carrying out wavelet packet transform on the collected signal, and calculating a wavelet packet coefficient energy value as a characteristic parameter; step (3) utilizing a quantum particle swarm optimization algorithm to optimize a regularization parameter and kernel parameter of vector-valued regularized kernel function approximation, and training a fault diagnosis model; and step (4) utilizing the trained diagnosis model to recognize circuit faults.
Test apparatus, test method, calibration device, and calibration method
Provided is a test apparatus including an optical test signal generating section that generates an optical test signal; an optical signal supplying section that supplies the optical test signal to a device under test that is a testing target among a plurality of the devices under test; a first optical switch section that selects, from among optical signals output by the plurality of devices under test, the optical signal output by the device under test that is the testing target; and an optical signal receiving section that receives the selected optical signal.
Test apparatus, test method, calibration device, and calibration method
Provided is a test apparatus including an optical test signal generating section that generates an optical test signal; an optical signal supplying section that supplies the optical test signal to a device under test that is a testing target among a plurality of the devices under test; a first optical switch section that selects, from among optical signals output by the plurality of devices under test, the optical signal output by the device under test that is the testing target; and an optical signal receiving section that receives the selected optical signal.
SIGNAL PATH MONITOR
A method for testing a signal path in a sensor, the signal path including a filter circuit and a comparator circuit, the method including: closing a first signal line that is arranged to bypass a first capacitor in the filter circuit; injecting a test signal into the signal path after the first signal line is closed; and detecting whether a signal that is output by the comparator circuit in response to the test signal satisfies a predetermined condition.
Partitioned force-sense system for test equipment
A force-sense system for providing signals to, or receiving signals from, a device under test (DUT) at a first DUT node. The system can include an interface coupling first and second portions of a first force-sense measurement device, such as a parametric measurement unit. The first and second portions of the first force-sense measurement device can be provided using respective different integrated circuits, such as can comprise different semiconductor dies of different die types. In a first test mode, the interface can be configured to communicate a first DUT force signal from the first portion to the second portion of the first force-sense measurement device, and in a second test mode the interface can be configured to communicate DUT sense information, received from the DUT at the first DUT node, from the second portion to the first portion of the first force-sense measurement device.
Signal path monitor
A method for testing a signal path in a sensor, the signal path including a filter circuit and a comparator circuit, the method including: closing a first signal line that is arranged to bypass a first capacitor in the filter circuit; injecting a test signal into the signal path after the first signal line is closed; and detecting whether a signal that is output by the comparator circuit in response to the test signal satisfies a predetermined condition.
Signal path monitor
A method for testing a signal path in a sensor, the signal path including a filter circuit and a comparator circuit, the method including: closing a first signal line that is arranged to bypass a first capacitor in the filter circuit; injecting a test signal into the signal path after the first signal line is closed; and detecting whether a signal that is output by the comparator circuit in response to the test signal satisfies a predetermined condition.
Digital output monitor circuit and high frequency front-end circuit
A digital output monitor circuit includes a first digital circuit that performs mutual conversion between serial data and parallel data, a second digital circuit that decodes data output from the first digital circuit and generates a control signal for an analog circuit, and a third digital circuit that converts at least the control signal for an analog circuit into digital data. The first digital circuit converts the data output from the third digital circuit into serial data and outputs as an output data signal.
Digital output monitor circuit and high frequency front-end circuit
A digital output monitor circuit includes a first digital circuit that performs mutual conversion between serial data and parallel data, a second digital circuit that decodes data output from the first digital circuit and generates a control signal for an analog circuit, and a third digital circuit that converts at least the control signal for an analog circuit into digital data. The first digital circuit converts the data output from the third digital circuit into serial data and outputs as an output data signal.