An integrated circuit includes first to n.sup.th metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to n.sup.th metal layers. The test circuit includes first to n.sup.th test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to n.sup.th metal layers, and n is a natural number.

An embodiment of a method for operating a modular test bench is disclosed, wherein the modular test bench comprises at least one test module to test a test object. The method comprises receiving first information on a hardware revision and on a software revision of the test module and receiving second information on a hardware revision and on a software revision of the test object. The method further comprises determining, if the combination of the first information and the second information fulfills a predetermined criterion and outputting a check signal, enabling the use of the test bench if the combination of the first information and the second information fulfills the predetermined criterion.

The present invention relates to: a spectral leakage-based loopback method for a built-in self-test (BIST), achieving cost efficiency by accurately predicting the nonlinearity of a mixed-signal circuit in a loopback mode; and a system therefor, the method comprising the steps of: modeling a correlation by deriving the transfer function of a loopback path; generating a digitally synthesized single-tone sine wave input signal by means of an on-chip DSP core so as to sample same in a nonlinear DAC channel, and supplying a DAC output signal to a nonlinear ADC channel through an analog loopback path so as to measure each of the DAC channel and the ADC channel for a process test; and performing post-processing by means of the on-chip DSP core and predicting the harmonics of the two separate DAC and ADC channels.

An exemplary method of detecting a Trojan circuit in an integrated circuit is related to applying a test pattern comprising an initial test pattern followed by a corresponding succeeding test pattern to a golden design of the integrated circuit, wherein a change in the test pattern increases side-channel sensitivity; measuring a side-channel parameter in the golden design of the integrated circuit after application of the test pattern; applying the test pattern to a design of the integrated circuit under test; measuring the side-channel parameter in the design of the integrated circuit under test after application of the test pattern; and determining a Trojan circuit to be present in the integrated circuit under test when the measured side-channel parameters vary by a threshold.

An error rate measuring apparatus includes a data transmission unit that transmits a test signal of a known pattern and a parameter value defined by a communication standard to a device under test, and a bit error measurement unit that measures a bit error of a signal transmitted from the device under test. The data transmission unit sequentially changes the parameter value and transmits the parameter value to the device under test. The bit error measurement unit measures a bit error of a signal transmitted from the device under test corresponding to the parameter value. The error rate measuring apparatus further includes a discrimination unit that discriminates a parameter value at which the number of bit errors is the least in a measurement result of the bit error measurement unit, as an optimum value of emphasis of an output waveform of the device under test.

A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.

A load testing device includes a connection unit to which a power source being tested is connected, a hydrogen generating unit that performs electrolysis based on power supplied from the power source being tested to generate hydrogen, two or more supply units to which hydrogen obtained in the hydrogen generating unit passes and to which a portable tank is removably attached, and an operational unit that has a load amount adjustment switch and a display unit. The load amount of the hydrogen generating unit is switched depending on an operational state of the load amount adjustment switch. The display unit displays at least one of an attachment status of the portable tank and a filling status of hydrogen in the two or more supply units.

It is possible to know a guideline for adjusting the levels of three voltage thresholds of a PAM4 signal. An error detection device receives a measurement pattern including a pseudo random pattern having equal appearance frequencies of four levels, decodes the measurement pattern into a most significant bit sequence signal MSB and a least significant bit sequence signal LSB, based on three voltage thresholds Vth1, Vth2, and Vth3, identifies and counts, by a level counting unit, the four levels of the measurement pattern, based on the most significant bit sequence signal MSB and the least significant bit sequence signal LSB, and displays numerical values or bar graphs indicating ratios of the appearance frequencies of the four levels of the measurement pattern so as to be in the same order as waveform levels of the measurement pattern, based on a result of the counting.

Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.

A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.