Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and/or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output pre-selected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit.

A force-sense system for providing signals to, or receiving signals from, a device under test (DUT) at a first DUT node. The system can include an interface coupling first and second portions of a first force-sense measurement device, such as a parametric measurement unit. The first and second portions of the first force-sense measurement device can be provided using respective different integrated circuits, such as can comprise different semiconductor dies of different die types. In a first test mode, the interface can be configured to communicate a first DUT force signal from the first portion to the second portion of the first force-sense measurement device, and in a second test mode the interface can be configured to communicate DUT sense information, received from the DUT at the first DUT node, from the second portion to the first portion of the first force-sense measurement device.

Systems, computer-implemented methods, and computer program products to facilitate external port measurement of qubit port responses are provided. According to an embodiment, a computer-implemented method can comprise terminating, by a system operatively coupled to a processor, one or more qubit ports with different electrical connections. The computer-implemented method can also comprise determining, by the system, one or more qubit port responses from external port responses based on the terminating. In some embodiments, the computer-implemented method can further comprise determining, by the system, a multiport admittance function corresponding to at least two of the one or more qubit ports.

An injection device is disclosed herein. The injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a base, a reservoir, a first testing pipe, a cleaning pipe and a liquid-draining pipe. The reservoir set on the base is provided with at least one connecting port and a dropping port, wherein the dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to at least one connecting port, wherein a first liquid is injected from the first testing pipe into the reservoir, and wherein the a cleaning liquid is injected from the cleaning pipe into the reservoir to clean the reservoir and the test area. The dropping port is utilized to drain off the first testing liquid and the cleaning liquid in the reservoir. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.

An injection device is disclosed herein. The injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a base, a reservoir, a first testing pipe, a cleaning pipe and a liquid-draining pipe. The reservoir set on the base is provided with at least one connecting port and a dropping port, wherein the dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to at least one connecting port, wherein a first liquid is injected from the first testing pipe into the reservoir, and wherein the a cleaning liquid is injected from the cleaning pipe into the reservoir to clean the reservoir and the test area. The dropping port is utilized to drain off the first testing liquid and the cleaning liquid in the reservoir. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.

Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.

A force-sense system for providing signals to, or receiving signals from, a device under test (DUT) at a first DUT node. The system can include an interface coupling first and second portions of a first force-sense measurement device, such as a parametric measurement unit. The first and second portions of the first force-sense measurement device can be provided using respective different integrated circuits, such as can comprise different semiconductor dies of different die types. In a first test mode, the interface can be configured to communicate a first DUT force signal from the first portion to the second portion of the first force-sense measurement device, and in a second test mode the interface can be configured to communicate DUT sense information, received from the DUT at the first DUT node, from the second portion to the first portion of the first force-sense measurement device.

Systems for probing superconducting circuits, including using a non-magnetic cryogenic heater, are disclosed. A system including a circuit board having a socket and a heater, mounted on the socket, is provided. The heater includes a resistive element and an arrangement for connection with wires configured to supply a current to the resistive element, where the heater is non-magnetic. The system further includes an integrated circuit package, mounted on the socket, such that the heater is located between the socket and the package, where the integrated circuit comprises superconducting circuits having a first temperature corresponding to a superconducting transition temperature. The heater is configured to raise a temperature associated with the integrated circuit from a second temperature to the first temperature, where the second temperature is lower than the first temperature, and where each of the first temperature and the second temperature is a cryogenic temperature.

An apparatus for determining a single decision function is configured to obtain measurements from a plurality of devices under test corresponding to stimulating signals applied to the plurality of devices under test. The stimulating signals correspond to a set of tests performed on the plurality of devices under test. The apparatus may further determine a subset of tests from the set of tests, such that the subset of tests is relevant for indicating whether the plurality of devices under test pass the set of tests. The apparatus may also determine the single decision function applicable to measurements from an additional device under test tested using the subset of tests, such that the single decision function is adapted to predict a test result for the set of tests on the basis of the subset of tests.

In-chip decoupling capacitor circuits refer to decoupling capacitors (DCAPs) that are placed on a chip. These DCAPs are generally used to manage power supply noise for the chip, and can be utilized individually or as a distributed system. In some cases, DCAPs may make up a significant portion of the chip. Unfortunately, defects in DCAPs will degrade over time, will encroach into active logic, and will further cause automatic test pattern generation (ATPG) failure. To date, there has been a lack of structural test coverage for DCAP circuits, which reduces test coverage of the chip as a whole. To this end, defects on the chip as they relate to DCAPs (i.e. shorts in the DCAP) may not be detected. The present disclosure provides a structural test system and method for DCAPs and other passive logic components located on-chip.