Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.

Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector.

A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.

This disclosure relates to signal observability rating. In an example, a method can include propagating a clock signal through a respective module of a circuit design in a forward and backward direction, evaluating clock signal propagation results for the respective module based on a forward and backward clock signal propagation of the clock signal to compute an observability rating for a data signal to be processed by the respective module during formal verification, and updating a current observability rating of the respective property for the data signal to the computed observability rating.

A chip verification system includes a plurality of agent modules, a register model, and a scoreboard module. The register model includes a register database, a plurality of access modules, and a return module. Each access module corresponds to one of a plurality of attribute parameters. Each agent module transmits an address code of its sequence to the return module. The return module obtains, according to the received address code, an address subject and the attribute parameter corresponding to the received address code from the register database, and outputs the obtained attribute parameter. Each driver module calls, according to the received attribute parameter, the corresponding access module to perform an operation on registers of DUT circuit according to a read write command of the sequence. The scoreboard module records each performed operation to generate an operation record, and outputs a verification result according to the operation record and data in registers.

The present invention pertains to a method of verifying a design of an integrated circuit. The methods executes an iteration of simulation test cycle using a digital representation of the design. Next, the method obtains simulation results from the iteration of the simulation test cycle and calculates, during the simulation test cycle, a test coverage value associated with the simulation results of the iteration of the simulation test cycle. If the test coverage value is less than a target value, the method determines if the simulation test cycle fails to satisfies an iteration limiting metric. If the simulation test cycle satisfies the iteration limiting metric, the method, dynamically adjusts one or more simulation test cycle parameter during the simulation test cycle and iterates the simulation test cycle and recalculating the test coverage value until the test coverage value is at least the target value or the simulation test cycle fails to satisfy the iteration limiting metric. The method then out puts a result of the verification of the design.

A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.

Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Methods and systems for performing fault injection testing on an integrated circuit hardware design. The methods include: (a) receiving a raw fault node list identifying one or more fault nodes of the hardware design; (b) receiving information indicating a grouping of the fault nodes in the raw fault node list into a plurality of fault node groups, each fault node group comprising fault nodes that have a same effect on a failure mode of the hardware design; (c) generating a final fault node list based on the fault node groups; (d) selecting a set of fault injection parameters from the final fault node list, the set of fault injection parameters identifying at least one fault node in the final fault node list to fault; (e) performing a fault injection test on the hardware design by causing a fault to be injected into a simulation of the hardware design based on the selected set of fault injection parameters; (f) determining a result of the fault injection test; (g) storing the result of the fault injection test; and repeating (d) to (g) at least once.

A system and method are disclosed for assembling a testbench for evaluating electronic systems. The method includes assembling large testbenches by using verification features associated with functional components, automatically creating component connections, and statistically checking the testbench prior to generation and simulation. The system includes a computer system that implements the method.