Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector.

Provided are embodiments for circuit for detecting an open-wire condition for a differential input. Embodiments include a sensor, and a line replaceable unit (LRU) coupled to the sensor, wherein the LRU comprises a differential amplifier to provide a sensor output. Embodiments can also include a synchronous demodulator coupled to an output of the differential amplifier through an alternating current (AC) coupling network, wherein the synchronous demodulator is configured to receive the differential amplifier output and a reference signal at the synchronous demodulator signal input and reference input, and provide a synchronous demodulator output voltage to indicate an open-wire condition. Also provided are embodiments of a method for detecting an open-wire condition for a differential input.

A digital-to-analog converter (DAC) includes a switching network and built-in-self-test (BIST) circuitry. The DAC, in operation, generates analog output signals in response to input codes of a set of input codes of the DAC. The BIST circuitry sequentially applies codes of a determined subset of codes of the set of input codes to test the plurality of switches. The determined subset of codes has fewer codes than the set of input codes. The BIST circuitry detects failures of switches of the plurality of switches based on responses of the DAC to the applied codes. In response to detecting a failure of a switch, the BIST generates a signal indicating a failure of the switching network.

Systems, methods, and computer readable medium described herein relate to techniques for characterizing and/or anomaly detection in integrated circuits such as, but not limited to, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). In one example aspect of certain example embodiments, a fully digital technique relies on the pulse width of signals propagated through a path under test. In another example aspect, the re-configurability of the integrated circuit is leveraged to combine the pulse propagation technique with a delay characterization technique to yield better detection of certain type of Trojans and the like. Another example aspect provides for running the test through reconfigurable path segments in order to isolate and identify anomalous circuit elements. Yet another example aspect provides for performing the characterization and anomaly detection without requiring golden references and the like.

A signal processing apparatus detects a phase difference between two signals by applying the Lissajous figure and compensates for an error between the signals by recognizing a pattern, thereby easily detecting the phase difference between the signals.

An abnormality detection device includes: a coupling-capacitor having a first-end and a second-end coupled with a high-voltage circuit; a signal output unit; a signal extraction unit; and a signal input unit. The signal output unit is coupled with the first-end of the coupling-capacitor via a detection-resistor, and outputs an alternating-current inspection-signal. The signal extraction unit extracts the inspection-signal, as an extraction-signal, output between the detection-resistor and the coupling-capacitor. The signal input unit detects abnormality of insulation resistance of the high-voltage circuit based on a level of the inputted extraction-signal. The signal extraction unit includes a signal removing filter and a subtraction circuit. The filter removes a signal equal in frequency to the inspection-signal and passes low-frequency noises lower in frequency than the inspection-signal. The subtraction circuit outputs a differential signal, as the extraction-signal, between a signal having passed through the filter and a signal not having passed through the filter.

The present invention relates to a method for testing a device under test. A component of the device under test generates or receives a bus signal, wherein the bus signal comprises a first data signal or a second data signal, and wherein an amplitude of the first data signal is different from an amplitude of the second data signal. A measurement instrument measures an amplitude of the bus signal. Further, it is determined whether the bus signal comprises the first data signal or the second data signal, based on the measured amplitude of the bus signal.

Systems, methods, and computer readable medium described herein relate to techniques for characterizing and/or anomaly detection in integrated circuits such as, but not limited to, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). In one example aspect of certain example embodiments, a fully digital technique relies on the pulse width of signals propagated through a path under test. In another example aspect, the re-configurability of the integrated circuit is leveraged to combine the pulse propagation technique with a delay characterization technique to yield better detection of certain type of Trojans and the like. Another example aspect provides for running the test through reconfigurable path segments in order to isolate and identify anomalous circuit elements. Yet another example aspect provides for performing the characterization and anomaly detection without requiring golden references and the like.

The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK−) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK−) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.

A method of detecting leakage of a data qubit includes applying a first cross-resonance pulse to the data qubit, the data qubit including a first state and a second state; applying a first echo pulse to the data qubit temporally following the applied first cross-resonance pulse; applying a second cross-resonance pulse to the data qubit temporally following the applied first echo pulse, the second cross-resonance pulse being an inverted form of the first cross-resonance pulse; applying a second echo pulse to the data qubit temporally following the second cross-resonance pulse; and detecting a leakage associated with the data qubit using an ancilla qubit coupled to the data qubit based on application of the first and second cross-resonance pulses, and the first and second echo pulses.