In a quantum computer, quantum algorithms are performed by a qubit interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals that are generated digitally at baseband and sent, via asynchronous ports, to DACs that feed an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multi-tap delay line. The setting of the multi-tap delay line is determined by a function of the port's setup-and-hold time. This function is trained, via machine learning, to be applicable across a variety of ports.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

An integrated circuit device may include core circuitry, and a set of external interface buffer circuits coupled to the core circuitry. To improve test time and accuracy, as well as to simplify test procedures during voltage testing of the set of external interface buffer circuits, the integrated circuit device may include a test circuit and a combinational logic circuit coupled to the set of external interface buffer circuits. The combinational logic circuit is configured to combine a logic level of each of the external interface buffer circuits into a test signal, and the test circuit is configured to execute a voltage test on the set of external interface buffer circuits based on a logic level of the test signal.

Described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. A majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.

A high-speed signal subsystem testing system tests a processor transmitter and receiver coupled to a connector via a transmitter trace and a receiver trace, respectively. A transmitter test circuit on a testing board coupled to the connector compares a transmitter voltage received from the transmitter via the transmitter trace and the connector to a common mode voltage range and, in response to the transmitter voltage being outside the common mode voltage range, provides a transmitter trace issue signal. A receiver test circuit on the testing board coupled to the connector transmits a first test voltage towards the receiver, compares a second test voltage detected at the receiver test circuit in response to transmitting the first test voltage towards the receiver to a reference test voltage and, in response to the second test voltage being above the reference test voltage, provides a receiver trace issue signal.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

A high-speed signal subsystem testing system tests a processor transmitter and receiver coupled to a connector via a transmitter trace and a receiver trace, respectively. A transmitter test circuit on a testing board coupled to the connector compares a transmitter voltage received from the transmitter via the transmitter trace and the connector to a common mode voltage range and, in response to the transmitter voltage being outside the common mode voltage range, provides a transmitter trace issue signal. A receiver test circuit on the testing board coupled to the connector transmits a first test voltage towards the receiver, compares a second test voltage detected at the receiver test circuit in response to transmitting the first test voltage towards the receiver to a reference test voltage and, in response to the second test voltage being above the reference test voltage, provides a receiver trace issue signal.

An integrated circuit and an electronic device including the integrated circuit are provided. An integrated circuit includes a sequential logic circuit, which includes a first scan cell that is configured to receive a scan input, and a plurality of scan cells sequentially connected in series from the first scan cell, a control unit, which is configured to receive a selection signal including an output of each of the plurality of scan cells, and is further configured to output a control signal responsive to the selection signal, and a monitoring circuit, which is configured to receive the control signal, is configured to perform first monitoring of first data at a first node that is an observation node in the sequential logic circuit responsive to the control signal, and is configured to output a result of the first monitoring to a monitoring node.

A display panel test circuit includes a first transistor connected to a first data line and receiving a red lighting test signal, a second transistor connected to the first data line and receiving a blue lighting test signal, a third transistor connected to a second data line and receiving a first green lighting test signal, a fourth transistor connected to a third data line and receiving the red lighting test signal, a fifth transistor connected to the third data line and receiving the blue lighting test signal, a sixth transistor connected to a fourth data line and receiving a second green lighting test signal, a seventh transistor connected to the second data line and receiving a crack test signal, and an eighth transistor connected to the fourth data line and receiving the crack test signal. The display panel test circuit performs one or more tests on a display panel.