An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.

An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.

This disclosure provides methods and apparatuses for testing a tested circuit. In an implementation, a chip test circuit transmits input data of a test vector to a data distribution circuit through an input of a test bus, and transmits the input data of the test vector to a scan input channel of a tested circuit through the data distribution circuit. After scanning of the tested circuit ends, output data of the test vector of the scan output channel of the tested circuit is transmitted to an output of the test bus through the data distribution circuit to complete the test of the tested circuit. A dynamic correspondence between the data distribution circuit and the test bus is implemented by configuring a first selector, so that test resources can be dynamically allocated.

A test circuit transmits input data of a test vector to a data distribution circuit using an input of a test bus, and transmits the input data of the test vector to a scan input channel in a circuit under test using the data distribution circuit. After scan of the circuit under test is completed, output data of the test vector on a scan output channel in the circuit under test is transmitted to an output of the test bus using the data distribution circuit, to complete testing of the circuit under test. A dynamic correspondence between the data distribution circuit and the test bus may be configured based on a specific test solution, so that a test resource can be dynamically allocated.

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer’s system. Additional embodiments are also provided and described in the disclosure.

An I/O control circuit includes a plurality of IO cells including an input section for stimulating a plurality of (n) pins of a device under test (DUT) and an output section for processing data output by the pins. The input section of each cell includes a latched driver each including a driver input, a first driver output, a next state driver output, and a current source. The next state driver output and current source are for coupling to drive the pins, and the latched drivers are serially connected with the first driver output of an earlier IO cell connected to the driver input of a next IO cell. The output section of each cell includes an analog to digital converter (ADC) for coupling to the n pins, and a memory element coupled to an output of the ADC.