An integrated circuit includes first to n.sup.th metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to n.sup.th metal layers. The test circuit includes first to n.sup.th test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to n.sup.th metal layers, and n is a natural number.

A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.

Various embodiments relate to a skew detector circuit, including: a logic circuit having two inputs configured to generate a logic 1 output when the two inputs have a logic 0 value and generator a logic 0 output when the two input have a logic 1 value; a first level shifter configured to increase the output of the logic circuit to a higher voltage; a second level shifter configured to increase the output of the first level shifter to a higher voltage; and a voltage regulator configured to produce a first voltage for the logic circuit, a second voltage for the first level shifter, and a third voltage for the second level shift.

A time error vector is determined using pairs of two closest points of input-referred noise data that straddle respective crossing times indicating when a clock signal representation crosses a threshold value, a slew rate of the clock signal representation, and the crossing times. A system filter is applied to the time error vector in the frequency domain. A first RMS value is determined indicating a jitter value present in the filtered time error vector. A raw clock signal time error vector of the clock signal under test is generated, the system filter is applied to the raw clock signal time error vector in the frequency domain, and a second RMS value indicating a jitter content of the filtered raw clock signal time error vector is determined. The second RMS value is corrected using the first RMS value to thereby generate a jitter measurement compensated for input-referred noise.

In a quantum computer, quantum algorithms are performed by a qubit interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals that are generated digitally at baseband and sent, via asynchronous ports, to DACs that feed an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multi-tap delay line. The setting of the multi-tap delay line is determined by a function of the port's setup-and-hold time. This function is trained, via machine learning, to be applicable across a variety of ports.

Semiconductor devices that include test circuitry to measure internal signal wire propagation delays during memory access operations, and circuity configured to store delay information that is used to configure internal delays based on the measured internal signal propagation circuit delays. The semiconductor device includes a test circuit configured to measure a signal propagation delay between a command decoder and a bank logic circuit based on time between receipt of a test command signal directly from the command decoder and a time of receipt of the test command signal routed through the bank logic circuit.

Embodiments of the present invention provide an automated test equipment (a “tester”) for testing a device under test, including a bidirectional dedicated real-time handler interface. Some embodiments include an interface having a trigger function, a fixed endpoint interface, an interface arranged on a test head, and/or a number of lines/communication channels adapted to a specific communication task, without separate signal lines, for example. The bidirectional dedicated real-time handler interface can be used to transmit thermal control signals, and the transmitted signals can be test site specific. The real-time signaling advantageously improves testing accuracy and efficiency.

The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

A test and measurement instrument includes one or more ports including at least one test port configured to couple to one or more devices under test, a user interface to receive one or more user inputs, an acquisition memory to store waveform data acquired from the one or more devices under test, one or more processors configured to execute code that causes the one or more processors to: receive an input through the user interface; determine one or more requested data types based on the input; transform the waveform data into compressed data containing only data elements corresponding to the one or more requested data types; and transmit the compressed data to a client. A method of providing usage-aware compressed data from a test and measurement instrument includes acquiring waveform data from one or more devices under test, receiving a user input through a user interface, determining one or more requested data types based on the user input, transforming the waveform data into compressed data containing only data elements corresponding to the one or more requested data types, and transmitting the compressed data to a client.