The present disclosure relates to a test response compaction scheme and, more particularly, to a test response compaction scheme for integrated circuits with improved diagnostic capability and test time, with related structures and processes. The method includes: arranging bits of a memory cell into channels and clock cycles, wherein each clock cycle is assigned a successive prime number and each channel has a maximum chain length of X number of bits; performing a test by applying stimulus and capturing response in memory elements; scanning out test results of the test performed on the bits for each cycle and channel; calculating a final signature of the test results using the successive prime number and a weighting afforded to each channel; and identifying any failures of the bits by comparing the final signature to an expected signature.

Scan forest can effectively compress test data volume, however, CPU time and memory consumption must be well-controlled to handle industrial designs. The present disclosure provides a method to establish a scan forest, which reduces memory consumption and CPU time significantly. A new low-power test application scheme is proposed, which does not need to increase the test application cost but can be of help to compress test data volume. Another new test application algorithm is proposed to reduce capture cycle power and shift cycle power by just doubling the test application time, which does not sacrifice the test data compression performance.

Described herein is a method implemented by circuitry for providing fault tolerance in a combinational circuit. The circuitry identifies sensitive gates of the circuit that require protection from at least one of a first type of fault and a second type of fault. Further, circuitry computes for each first type of transistor included in the sensitive gate, a first failure probability, and for each second type of transistor included in the sensitive gate, a second failure probability. The circuitry calculates a first parameter corresponding to a number of the first type of transistors for which the computed first failure probabilities exceed a first predetermined threshold and a second parameter corresponding to a number of second type of transistors for which the computed second failure probabilities exceed a second predetermined threshold to determine a protection type based on an area overhead constraint.

A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.